Back to results
US 2006/0242521 A1Published application
Built-in self-test arrangement for integrated circuit memory devices
AssigneeTexas Instruments Incorporated
InventorsKuong Hii, Danny Cline, Theo Powell
Life of this patent
Estimating the term…
Abstract
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
Claims6
An integrated circuit including a memory array and test circuitry, the test circuitry comprising:
- a memory circuit containing a plurality of test algorithms;
- logic circuitry having an input coupled to the memory circuit, the logic circuitry comprising:
- a memory logic which receives test instructions output from the memory circuit, processes the instructions, and produces a plurality of output signals;
- register circuitry which stores the output signals;
- a test circuit receiving the output signals stored in register;
- and
- wherein in response to a write instruction from the memory circuit the test circuit receives data read from the memory array and compares the data read from the memory array with expected data, and outputs a result signal representative of the comparison.
4 more elements
Dependencies are inferred from the claim text.