Multiple uses for bist test latches
AssigneeInternational Business Machines Corporation
InventorsSteven Ferguson, Garrett Koch, Osamu Takahashi, Michael White
Life of this patent
Estimating the term…
Abstract
A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
Claims19
A method for efficient multipurpose use of built-in self test (BIST) test latches in testing arrays of a processor, comprising:
- configuring a plurality of latches to operate as array built-in self test (ABIST) shadow latches to test the arrays;
- and
- reconfiguring the plurality of latches to operate as logic built-in self test (LBIST) observation latches to test the arrays.
An apparatus for efficient multipurpose use of built-in self test (BIST) test latches in testing at least one array of a processor, comprising:
- a plurality of latches that are at least configured to operate in an ABIST mode and at least configured to operate in an LBIST mode;
- and
- a plurality of connected latches each of the plurality of connected latches is at least configured to be coupled to at least one latch of the plurality of latches and at least configured to be coupled to the at least one array.
A computer program product for efficient multipurpose use of built-in self test (BIST) test latches in testing arrays of a processor, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:
- computer code for configuring a plurality of latches to operate as automatic built-in self test (ABIST) shadow latches to test the arrays;
- and
- computer code for reconfiguring the plurality of latches to operate as logic built-in self test (LBIST) observation latches to test the arrays.
A processor for efficient multipurpose use of built-in self test (BIST) test latches in testing arrays of a processor, the processor including a computer program comprising:
- computer code for configuring a plurality of latches to operate as automatic built-in self test (ABIST) shadow latches to test the arrays;
- and
- computer code for reconfiguring the plurality of latches to operate as logic built-in self test (LBIST) observation latches to test the arrays.
Dependencies are inferred from the claim text.