Systematic scan reconfiguration
AssigneeLSI Logic Corporation
InventorsAhmad Alvamani, Narendra Devta-Prasanna, Arun Gunda
Life of this patent
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Abstract
Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for the selected decoder configuration. When F=Ø, a set of patterns Pi is reported for each decoder configuration iεC, where C is a set of selected decoder configurations.
Claims20
A method for implementing test generation for systematic scan reconfiguration in an integrated circuit, comprising steps of:
- adding all detectable faults of said integrated circuit to a set F;
- starting with a SAS decoder configuration;
- generating ATPG patterns for said faults in said set F for a selected decoder configuration;
- and
- when F=Ø, reporting a set of patterns Pi for each decoder configuration iεC, where C is a set of selected decoder configurations.
A method for implementing test application for systematic scan reconfiguration in an integrated circuit, comprising steps of:
- selecting a configuration i from a set of configurations C;
- selecting a test pattern j from a set of patterns Pi;
- loading a group address into a SAS decoder by setting care bits of said group address to an unselected combination;
- loading a test vector corresponding to segments of a selected group while unloading old contents of said segments to an output compressor;
- and
- when at least one combination of care bits is not selected, returning to said step of loading a group address.
A computer-readable medium having computer-executable instructions for performing a method for implementing test generation for systematic scan reconfiguration in an integrated circuit, said method comprising steps of:
- adding all detectable faults of said integrated circuit to a set F;
- starting with a SAS decoder configuration;
- generating ATPG patterns for said faults in said set F for a selected decoder configuration;
- and
- when F=Ø, reporting a set of patterns Pi for each decoder configuration iεC, where C is a set of selected decoder configurations.
A computer-readable medium having computer-executable instructions for performing a method for implementing test application for systematic scan reconfiguration in an integrated circuit, said method comprising steps of:
- selecting a configuration i from a set of configurations C;
- selecting a test pattern j from a set of patterns Pi;
- loading a group address into a SAS decoder by setting care bits of said group address to an unselected combination;
- loading a test vector corresponding to segments of a selected group while unloading old contents of said segments to an output compressor;
- and
- when at least one combination of care bits is not selected, returning to said step of loading a group address.
Dependencies are inferred from the claim text.