Method and apparatus for generating expect data from a captured bit pattern, and memory device using same

A synchronization circuit of a memory device, comprising:

• a memory bus to which digital signals are applied;
• a latch coupled to the memory bus, the latch configured to receive and capture a plurality of digital signals representing a stream of data;
• a pattern generator coupled to the latch, the pattern generator configured to receive a predetermined sampling of data, and in response operable to generate groups of expected digital signals, each group of expected digital signals having a value determined in response to the value of the previous group of expected digital signals;
• and
• a comparison circuit coupled to receive the plurality of digital signals from the latch and the groups of expected digital signals from the pattern generator, the comparison circuit operable to compare the plurality of digital signals to the expected digital signals to determine the plurality of digital signals were properly captured.

A synchronization circuit operable in a synchronization mode to determine if applied signals on a memory bus are properly captured by a memory device, comprising:

• a clock generator circuit having an input for receiving an external clock signal, the clock generator circuit operable to generate an internal clock signal having a phase relative to the external clock signal;
• a latch coupled to receive the internal clock signal from the clock generator and having a plurality of input and output terminals, the latch operable to capture at least a first group of signals applied on the memory bus and a second group of signals applied after the first group of signals responsive to the internal clock signal;
• a pattern generator configured to receive the internal clock signal from the clock generator, the pattern generator operable to generate groups of expected signals from the captured first group of applied signals;
• and
• an evaluation circuit coupled to receive the groups of applied signals from the latch and the groups of expected signals from the pattern generator, the evaluation circuit configured to determine that the second group of applied signals was properly captured in response to the second captured group of applied signals corresponding to the generated group of expected signals.

A synchronization circuit for synchronizing an external clock signal applied on a clock terminal of a memory device, comprising:

• a clock generator circuit having an input configured to receive the external clock signal, the clock generator circuit operable to generate an internal clock signal having a phase relative to the external clock signal;
• a register circuit having at least one register configured to receive groups of digital signals and the internal clock signal from the clock generator, the register circuit operable to latch the digital signals responsive to the internal clock signal;
• a pattern generator circuit having a plurality of inputs configured to receive a clock signal and an initialization signal corresponding to a subset of a first group of digital signals received by the register circuit, the pattern generator circuit operable to generate expected digital signals representing a bit stream of expected data responsive to the clock signal and initialization signal;
• an evaluation circuit coupled to the register circuit and the pattern generator, the evaluation circuit operable to receive and compare the bit stream of expected data to a second group of digital signals provided by the register circuit and to repeat the comparison to determine successful capture of groups of digital signals when matched to the bit stream of expected data, the evaluation circuit further operable to generate a result signal based on each comparison;
• and
• a control circuit coupled to the clock generator circuit, the pattern generator and the evaluation circuit, the control circuit configured to receive and latch the result signals for all the comparisons by the evaluation circuit, the control circuit operable to determine an optimal result signal from the stored result signals and generate a control signal in response to the optimal result signal for adjusting the phase of the internal clock signal to synchronize the internal clock signal to the external clock signal.

An integrated circuit having a plurality of external terminals adapted to receive respective signals, comprising:

• a clock terminal configured to receive an external clock signal;
• a clock generator circuit having an input coupled to the clock terminal, the clock generator circuit operable to generate an internal clock signal having a phase relative to the external clock signal in response to a phase command;
• a latch coupled to at least some of the external terminals and the clock generator circuit, the latch configured to receive and capture groups of digital signals having a repeating sequence of data bits applied on external terminals responsive to the internal clock signal, each group of digital signals applied on the external terminals at a given time designated a data word;
• a pattern generator having a clock terminal configured to receive at least one clock signal and having a control terminal configured to receive a seed signal having values determined in response to the groups of digital signals captured by the latch, the pattern generator configured to use the seed signal to seed an expected data pattern for the groups of digital signals applied on the external terminals;
• and
• an evaluation circuit coupled to the clock generator circuit, the latch and the pattern generator, the evaluation circuit during a synchronization mode configured to activate the seed signal from the pattern generator and thereafter deactivate the seed signal, the evaluation circuit further configured to compare the groups of digital signals stored by the latch to the expected data pattern generated by the pattern generator and to adjust the phase command to determine an optimum phase command from the results of the comparisons, the evaluation circuit further configured to apply the optimum phase command to the clock generator circuit during a normal operation mode.

A packetized memory device, comprising:

• a clock generator circuit operable to generate an internal clock signal relative to an external clock signal responsive to a phase command signal;
• at least one array of memory cells configured to store data at a location determined by a row address and a column address;
• a row address circuit configured to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit configured to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit configured to couple data between an external terminal and the column address circuit responsive to a third set of command signals;
• and
• a command buffer receiving command packets and initialization packets having a predetermined value, the command buffer further comprising:
• a latch circuit configured to latch the received command packets and initialization packets responsive to a transition of the internal clock signal, the latch circuit further configured to generate respective command words and initialization words corresponding to each received command packet and initialization packet, and to generate a seed signal that includes a sampling of data from the received command words and initialization words;
• a pattern generator having a clock terminal configured to receive at least one clock signal, the pattern generator further having a control terminal configured to receive the seed signal to seed an expected data pattern of a repeating bit sequence;
• and
• a synchronization circuit coupled to the clock generator circuit, the latch circuit and the pattern generator, the synchronization circuit during a synchronization operation configured to activate the seed signal and thereafter deactivate the seed signal, compare the command words and initialization words stored by the latch circuit to the expected data pattern generated by the pattern generator, and adjust the phase command to provide an optimum phase command from the results of the comparison, the synchronization circuit further configured to apply the optimum phase command to the clock generator circuit during a normal operation of the packetized memory device.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted allow data to be output from the computer system;
• and
• a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory, comprising,
• a clock generator circuit operable to generate an internal clock signal relative to an external responsive to a phase command signal;
• at least one array of memory cells configured to store data at a location determined by a row address and a column address;
• a row address circuit configured to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit configured to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit configured to couple data between an external terminal and the column address circuit responsive to a third set of command signals;
• a command buffer receiving command packets and initialization packets having a predetermined value, the command buffer further comprising a synchronization circuit, comprising:
• a latch configured to receive and capture the command packets and initialization packets responsive to a transition of the internal clock signal, the latch further configured to generate respective command words and initialization words that represent a stream of data corresponding to the received command packet and initialization packet;
• a pattern generator coupled to the latch, the pattern generator configured to receive a predetermined sampling of data, and in response operable to generate groups of expected data, each group of expected data having a value determined in response to the value of the previous group of expected data;
• and
• a comparison circuit coupled to the latch and pattern generator, the comparison circuit operable to receive and compare the groups of expected data to the latched stream of data to determine the stream of data was properly captured.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted allow data to be output from the computer system;
• and
• a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory, comprising,
• a clock generator circuit operable to generate an internal clock signal relative to an external responsive to a phase command signal;
• at least one array of memory cells configured to store data at a location determined by a row address and a column address;
• a row address circuit configured to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit configured to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit configured to couple data between an external terminal and the column address circuit responsive to a third set of command signals;
• and
• a command buffer receiving command packets and initialization packets having a predetermined value, the command buffer further comprising:
• a latch circuit configured to latch the received command packets and initialization packets responsive to a transition of the internal clock signal, the latch circuit further configured to generate respective command words and initialization words corresponding to each received command packet and initialization packet, and to generate a seed signal that includes a sampling of data from the received command words and initialization words;
• a pattern generator having a clock terminal configured to receive at least one clock signal, the pattern generator further having a control terminal configured to receive the seed signal to seed an expected data pattern of a repeating bit sequence;
• and
• a synchronization circuit coupled to the clock generator circuit, the latch circuit and the pattern generator, the synchronization circuit during a synchronization operation configured to activate the seed signal and thereafter deactivate the seed signal, compare the command words and initialization words stored by the latch circuit to the expected data pattern generated by the pattern generator, and adjust the phase command to provide an optimum phase command from the results of the comparison, the synchronization circuit further configured to apply the optimum phase command to the clock generator circuit during a normal operation of the packetized memory device.