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US 2006/0242511 A1Published application
High speed interconnect circuit test method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee Whetsel
Life of this patent
Estimating the term…
Abstract
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.
Claims3
A process of performing a test comprising:
- applying a test data signal at the input of an interconnect circuit, which has an output, at a defined time during an Update-DR state of a JTAG test access port controller;
- performing a sample of the test data signal at the interconnect circuit output under at least partial control of a JTAG test access port controller at a selectable time after the defined time, the selectable time occurring before a normal sample of the test data signal during a Capture-DR state of the controller that normally follows the Update-DR state;
- and
- preventing the normal sample of the test data signal at the output of the interconnect circuit under at least partial control of the JTAG test access port controller during the Capture-DR state that normally follows the Update-DR state.
1 more element
A process of performing a test comprising:
- applying a test data signal at the input of an interconnect circuit, which has an output, for a period of time starting at a defined time during an Update-DR state, occurring in a JTAG test access port controller, that is later followed by a Capture-DR state;
- performing a first sample of the test data signal at the interconnect circuit output under at least partial control of a JTAG test access port controller at a selectable time that is after the defined time and before the Capture-DR state;
- and
- performing a second sample of the test data signal at the output of the interconnect circuit under at least partial control of the JTAG test access port controller during the first Capture-DR state of the controller normally occurring after the Update-DR state.
1 more element
A method of testing an interconnect circuit between a first and second device comprising the steps of;
- applying, from the first device, a stimulus signal to the interconnect circuit;
- observing, in the second device, the transient response of the interconnect circuit to the stimulus signal under at least partial control of a JTAG test access port controller, and observing, in the second device, the steady state response of the interconnect circuit to the stimulus signal under at least partial control of a JTAG test access port controller.
Dependencies are inferred from the claim text.