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US 2006/0242507 A1Published application
Achieving Desired Synchronization at Sequential Elements While Testing Integrated Circuits Using Sequential Scan Techniques
AssigneeTexas Instruments Incorporated
InventorsYatin ACHARYA, Anand BHAT
Life of this patent
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Abstract
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG)). Due to the programmability of delay magnitude, the burden on a designer to achieve synchronization of the data input with the clock signal while testing, is reduced.
Claims6
An integrated circuit comprising:
- a plurality of sequential elements coupled in sequence for testing according to a sequential scan technique, said plurality of sequential elements containing a first sequential element;
- and
- a delay circuit provided in a path to said first sequential element, said delay circuit being programmable to provide a desired delay magnitude such that a data input is received synchronous with a clock input at said first sequential element.
Dependencies are inferred from the claim text.