US 2006/0242505 A1 · APPARATUS FOR PERFORMING STUCK FAULT TESTINGS WITHIN AN INTEGRATED CIRCUIT

Abstract

An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select signals, and the second select register generates a set of complement encoded select signals. Coupled to the first and second select registers, the decoder decodes the set of true encoded select signals and the set of complement encoded signals for controlling the chain of multiplexors. Each multiplexor within the chain of multiplexors is connected to one of the outputs of the decoder. The chain of multiplexors generates a single output value based on the set of select signals.

Claims18

Dependent claims

An apparatus for performing level-sensitive scan design (LSSD) tests, said apparatus comprising:

a first select register for generating a set of true encoded select signals from a set of select signals;
a second select register for generating a set of complement encoded select signals from said set of select signals;
a decoder, coupled to said first and second select registers, for receiving said set of true encoded select signals and said set of complement encoded signals, wherein said decoder includes a plurality of outputs;
and
a plurality of multiplexors connected in series, wherein each of said plurality of multiplexors is connected to one of said plurality of outputs from said decoder, wherein said plurality of multiplexors generate a single output value based on said set of select signals.

2 more elements

Dependencies are inferred from the claim text.

Apparatus for performing stuck fault testings within an integrated circuit

Life of this patent

Apparatus for performing stuck fault testings within an integrated circuit

Life of this patent

Abstract

Claims18