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US 2006/0242503 A1Published application
Integrated circuit test system
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorYoji Masuda
Life of this patent
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Abstract
A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by software, generates, based on expanded data, a pulse waveform, and outputs the generated pulse waveform.
Claims8
An integrated circuit test system comprising:
- a frame processor provided for each pin of an integrated circuit for generating, based on test pattern data corresponding to the pin, a signal waveform to be sent to the pin;
- a pin electronics for sending a signal corresponding to the signal waveform to each pin;
- and
- a pattern data memory for storing compression test pattern data obtained by compressing the test pattern data,
- wherein the frame processor generates the signal waveform while expanding the compression test pattern data.
2 more elements
Dependencies are inferred from the claim text.