Built-in self-testing of multilevel signal interfaces

A method performed in a memory system including a memory control device having a first multilevel signal interface, a memory device having a second multilevel signal interface, and signal pathways coupling the first multilevel signal interface to the second multilevel signal interface, the method comprising:

• generating first binary test signals;
• encoding the first binary test signals into multilevel signals having more than two signal levels;
• transmitting the multilevel signals from one of the memory control device and the memory device to another one of the memory control device and the memory device;
• decoding the multilevel signals into second binary test signals;
• generating binary reference signals;
• and
• comparing the second binary test signals with the binary reference signals to detect possible errors in at least one of the first multilevel signal interface, and second multilevel signal interface, and the signal pathways.

A method performed in a memory system including a memory control device having a first multilevel signal interface, a memory device having a second multilevel signal interface, and signal pathways coupling the first multilevel signal interface to the second multilevel signal interface, the method comprising:

• generating first binary test signals;
• encoding the first binary test signals into first multilevel signals having more than two signal levels;
• transmitting the first multilevel signals from the memory control device to the memory device;
• transmitting second multilevel signals from the memory device to the memory control device, the second multilevel signals being derived from the first multilevel signals;
• decoding the second multilevel signals into second binary test signals;
• generating binary reference signals;
• and
• comparing the second binary test signal with the binary reference signals to detect possible errors in at least one of the first and second multilevel signal interface.

A memory system disposed on a motherboard, the memory system comprising:

• a. a signal pathway extending as a trace on the motherboard;
• b. a memory controller having integrated thereon:
• i. a test-signal generator to generate a test signal;
• ii. a master signal interface containing a master transmit mechanism and a master receive mechanism, wherein the master transmit mechanism is coupled between the test-signal generator and the signal pathway and is to transmit a first signal derived from the test signal to the signal pathway;
• and
• iii. an error detector coupled to the master receive mechanism;
• and
• c. a memory module coupled to the memory controller via the signal pathway, the memory module including:
• i. memory;
• ii. a slave signal interface disposed between the signal pathway and the memory, the slave signal interface including a slave transmit mechanism and a slave receive mechanism, wherein the slave receive mechanism is to receive the first signal from the memory controller and the slave transmit mechanism is to transmit a second signal related to the first signal to the memory controller via the signal pathway;
• and
• iii. wherein the master receive mechanism is to receive the second signal from the memory module and the error detector is to compare a third signal derived from the second signal to a reference signal generated in the memory controller and to output an error signal in response to a mismatch between the third signal and the reference signal.