Programmable in-situ delay fault test clock generator
AssigneeCisco Technology, Inc.
InventorsHong-Shin Jun, Sung Chung, Heon Kim
Life of this patent
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Abstract
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.
Claims20
A system for generating a launch and capture clocks, the system comprising
- a delay clock generator for generating one or more clocks with delay with respect to a system clock;
- a pulse Programmable Selection Generator (PSG) for generating a sequence in which the clocks are to be selected, the clocks being selected with a delay;
- and
- a multiplexer for selecting the plurality of clocks based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.
A method for generating a launch and capture clocks, the method comprising
- generating one or more clocks with delay with respect to a system clock;
- generating a sequence in which the clocks are to be selected, clocks being selected with a delay;
- and
- selecting the plurality of clocks based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.
A method for in-situ launch and capture clock generation for semiconductor device testing, the method comprising;
- generating one or more clocks with delay with respect to a system clock;
- selecting the sequence of the delay clocks based on pre-programmed values for pulse selection;
- selecting the plurality of clocks based on the selected sequence for generating launch and capture clocks;
- and
- adding extra wait time before a launch pulse and after a capture pulse for at least one of the clock cycles generated by the selected clocks.
A system for generating a launch and capture clocks, the system comprising
- means for generating one or more clocks with delay with respect to a system clock;
- means for generating a sequence in which the clocks are to be selected, the clocks being selected with a delay;
- and
- means for selecting the plurality of clocks based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.
An apparatus for generating a launch and capture clocks, the apparatus comprising
- a processing system including a processor coupled to a display and user input device;
- a machine readable medium including instructions for generating a launch and capture clocks for at-speed testing to detect faults in semiconductors devices, the medium comprising
- one or more instructions for generating one or more clocks with delay with respect to a system clock;
- one or more instructions for selecting the sequence of the delay clock based on pre-programmed values for pulse selection;
- one or more instructions for selecting one of the plurality of clocks based on the selected sequence for generating launch and capture clocks;
- and
- one or more instructions for adding extra wait time before the launch pulse and after the capture pulse for the multiple clock cycles.
A machine readable medium including instructions for generating a launch and capture clocks for at-speed testing to detect faults in semiconductors devices, the medium comprising
- one or more instructions for generating one or more clocks with delay with respect to a system clock;
- one or more instructions for selecting the sequence of the delay clock based on pre-programmed values for pulse selection;
- one or more instructions for selecting one of the plurality of clocks based on the selected sequence for generating launch and capture clocks;
- and
- one or more instructions for adding extra wait time before the launch pulse and after the capture pulse for the multiple clock cycles.
Dependencies are inferred from the claim text.