Encrypted JTAG interface

A method comprising:

• transmitting data from a test data in (TDI) line of a JTAG interface included in a system under test on a first line of a debug interface of the system under test for communicatively coupling the system under test to a debug device external to the system under test;
• receiving data on a second line of the debug interface of the system under test;
• providing the data received on the second line of the debug interface to a test data out (TDO) line, a test rest (TR) line, and a test mode state (TMS) line of the JTAG interface;
• receiving a clock signal on a clock line of the debug interface;
• and
• providing the clock signal on the test clock (TCLK) line of the JTAG interface.

A method comprising:

• transmitting data from a test data out (TDO) line, a test rest (TR) line, and a test mode state (TMS) of a JTAG interface included in a debug device on a first line of a debug interface of the debug device for communicatively coupling the debug device to a system under test;
• receiving data from a second line of the debug interface;
• providing the data received on the second line of the debug interface to the test data in (TDI) line of the JTAG interface;
• and
• transmitting a clock signal from a test clock (TCLK) line of the JTAG interface on a clock line of the debug interface.

Apparatus comprising:

• means for transmitting data from a test data in (TDI) line of a JTAG interface included in system under test on a first line of a debug interface of the system under test for communicatively coupling the system under test to debug device external to the system under test;
• means for receiving data on a second line of the debug interface of the system under test;
• means for providing the data received on the second line of the debug interface to a test data out (TDO) line, a test rest (TR) line, and test mode state (TMS) line of the JTAG interface;
• means for receiving a clock signal on a clock line of the debug interface;
• and
• means for providing the clock signal on the test clock (TCLK) line of the JTAG interface.

Apparatus comprising:

• means for transmitting data from a test data out (TDO) line, a test rest (TR) line, and test mode state (TMS) of a JTAG interface included in a debug device on a first line of a debug interface of the debug device for communicatively coupling the debug device to a system under test;
• means for receiving data from a second line of the debug interface;
• means for providing the data received on the second line of the debug interface to the test data in (TDI) line of the JTAG interface;
• and
• means for transmitting a clock signal from a test clock (TCLK) line of the JTAG interface on a clock line of the debug interface.