Clock control circuit
AssigneeOki Semiconductor Co., Ltd.
InventorHiroyuki Hanamori
Life of this patent
Estimating the term…
Abstract
A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.
Claims10
A clock control circuit built in a semiconductor integrated circuit including an input/output circuit for performing an input/output operation based on an external master clock signal, and a processor for performing control operation in accordance with a program, to generate a reference bus clock signal which is the basis for the operation of said processor, based on the master clock signal, said clock control circuit comprising:
- a divider unit which divides the master clock signal in response to a falling timing of the master clock signal to generate a divided clock signal;
- a multiplier unit which multiplies the frequency of the master clock signal by n (where n is an integer equal to or larger than three) to generate a multiplied signal synchronized to a rising timing of the master clock signal;
- a counter which is reset each time the master clock signal rises, and counts up one by one each time the multiplied signal rises;
- a comparator which outputs a comparison result signal at a first level when a count value of said counter is less than n−1, and sets the comparison result signal to a second level different from the first level when the count value is n−1;
- a logical OR gate which outputs a logical OR of the comparison result signal and the multiplied signal to output a multiplied clock signal;
- and
- a selector unit which selects one of the divided clock signal and the multiplied clock signal and outputs the selected signal as the reference bus clock signal.
A clock control circuit built in a semiconductor integrated circuit including an input/output circuit for performing an input/output operation based on an external master clock signal, and a processor for performing a control operation in accordance with a program, to generate a reference bus clock signal which is the basis for the operation of said processor, based on the master clock signal, said clock control circuit comprising:
- a divider unit which divides the master clock signal in response to a falling timing of the master clock signal to generate a divided clock signal;
- a multiplier unit which multiplies the frequency of the master clock signal by n (where n is an integer equal to or larger than three) to generate a multiplied signal synchronized to a rising timing of the master clock signal;
- a counter which is reset each time the master clock signal rises, and counts up one by one each time the multiplied signal rises;
- a comparator which outputs a comparison result signal at a first level when a count value of said counter is less than n−1, and sets the comparison result signal to a second level different from the first level when the count value is n−1;
- a logical OR gate which outputs a logical OR of the comparison result signal and the multiplied signal;
- a first selector which selects one of an output signal of said logical OR gate and the multiplied signal in accordance with a first selection signal, and outputs the selected signal as a multiplied bus clock signal;
- and
- a second selector which selects one of the divided clock signal and the multiplied bus clock signal in accordance with a second selection signal, and outputs the selected signal as the reference bus clock signal.
A clock control circuit built in a semiconductor integrated circuit including an input/output circuit for performing an input/output operation based on an external master clock signal, and a processor for performing a control operation in accordance with a program, to generate a reference bus clock signal which is the basis for the operation of said processor, based on the master clock signal, said clock control circuit comprising:
- a divider unit which divides the master clock signal in response to a falling timing of the master clock signal to generate a divided clock signal;
- a multiplier unit which multiplies the frequency of the master clock signal by n (where n is an integer equal to or larger than three) to generate a multiplied signal synchronized to a rising timing of the master clock signal;
- a counter which is reset each time the master clock signal rises, and counts up one by one each time the multiplied signal rises;
- a comparator which outputs a comparison result signal at a first level when a count value of said counter is less than n−1, and sets the comparison result signal to a second level different from the first level when the count value is n−1;
- a logical OR gate which outputs a logical OR of the comparison result signal and the multiplied signal;
- a first selector which selects an output signal of said logical OR gate and the multiplied signal in accordance with a first selection signal, and outputs the selected signal;
- a second selector which selects one of an output signal of said first selector and an inverted version of the output signal in accordance with a second selection signal, and outputs the selected signal as a multiplied clock signal;
- and
- a third selector which selects one of the divided clock signal and the multiplied clock signal in accordance with a third selection signal, and outputs the selected signal as the reference bus clock signal.
Dependencies are inferred from the claim text.