US 2006/0242394 A1 · Processor and processor instruction buffer operating method

Abstract

A processor includes an instruction fetch unit providing a fetch address to the memory system; a branch buffer, a normal buffer, and a general buffer, which receive fetch instructions, respectively; a to-be-issued instruction selecting unit, which selects an instruction from the normal buffer, the branch buffer, and the general buffer and issues the instruction in conformity with an instruction from the instruction buffer control unit; an instruction decoding unit, which receives the instruction issued from the to-be-issued instruction selecting unit, decodes the issued instruction, and transmits decoded results to the instruction buffer control unit; a loop processing unit, which receives the decoded results from the instruction decoding unit and transmits a loop start address to the instruction fetch unit; and a branch determination unit, which transmits a fetch address to the instruction fetch unit established when a branching condition is satisfied or not satisfied.

Claims20

Dependent claims

A processor comprising:

a memory system;
an instruction fetch unit, which provides a fetch address to the memory system;
a branch buffer, a normal buffer, and a general buffer, which receive fetch instructions from the memory system, respectively;
an instruction buffer control unit, which controls the instruction fetch unit, the branch buffer, the normal buffer, and the general buffer;
a to-be-issued instruction selecting unit, which selects an instruction from the normal buffer, the branch buffer, and the general buffer and issues the instruction in conformity with an instruction from the instruction buffer control unit;
an instruction decoding unit, which receives the instruction issued from the to-be-issued instruction selecting unit, decodes the issued instruction, and transmits decoded results to the instruction buffer control unit;
a loop processing unit, which receives the decoded results from the instruction decoding unit and transmits a loop start address to the instruction fetch unit;
and
a branch determination unit, which receives the decoded results from the instruction decoding unit and transmits a fetch address to the instruction fetch unit established when a branching condition is satisfied or not satisfied.

6 more elements

A processor instruction buffer operating method, comprising:

selecting, by a to-be-issued instruction selecting unit, an instruction from a normal buffer and a branch buffer and issuing the instruction in conformity with an instruction from an instruction buffer control unit;
determining whether a branching condition for an instruction issued by a branch determination unit is satisfied;
clearing the branch buffer by the instruction buffer control unit when the branching condition is not satisfied;
specifying an address to be issued next by the instruction buffer control unit as a branching target address when the branching condition is satisfied;
determining, by the instruction buffer control unit, whether there is an instruction in the branch buffer;
and
copying and moving the content of the branch buffer to the normal buffer in conformity with an instruction from the instruction buffer control unit, and at the same time selecting, by the to-be-issued selecting unit, an instruction from the branch buffer and issuing the instruction in conformity with an instruction from the instruction buffer control unit when the branching condition is satisfied.

4 more elements

A processor instruction buffer operating method, comprising:

selecting, by a to-be-issued instruction selecting unit, an instruction from a normal buffer and a loop buffer and issuing the instruction in conformity with an instruction from an instruction buffer control unit;
determining whether an instruction issued by a loop processing unit is a loop start instruction;
determining whether the loop processing unit initiates jumping from the tail end of a loop to the beginning thereof and a looping condition is satisfied when the branching condition is not satisfied;
jumping to the beginning of the loop and specifying an address to be issued next by the instruction buffer control unit as the loop start address when the branching condition is satisfied;
and
copying the content of the loop buffer and storing the content in the normal buffer in conformity with an instruction from the instruction buffer control unit, and at the same time selecting, by the to-be-issued selecting unit, an instruction from the loop buffer and issuing the instruction in conformity with an instruction from the instruction buffer control unit.

3 more elements

Dependencies are inferred from the claim text.

Processor and processor instruction buffer operating method

Life of this patent

Processor and processor instruction buffer operating method

Life of this patent

Abstract

Claims20