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US 2006/0242391 A1Published application
Context switching within a data processing system having a branch prediction mechanism
AssigneeArm Limited
InventorMatthew Elwood
Life of this patent
Estimating the term…
Abstract
A branch target buffer 10 is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries 12 within the branch target buffer 10 and those individual entries are invalidated.
Claims21
Apparatus for processing data under control of program instructions of variable length, said apparatus comprising:
- a memory operable to store said program instructions;
- a fetch unit operable to fetch blocks of program instructions to be added to a sequence of program instructions to be decoded from fetch addresses within said memory;
- and
- a branch target buffer operable to store a plurality of entries predicting fetch addresses of respective blocks of program instructions as containing a branch instruction to a branch target address, said branch target buffer being responsive to a fetch address of a block of program instructions being fetched from said memory by said fetch unit to detect a hit for an entry within said branch target buffer predicting that a branch instruction is present within said block of program instructions;
- wherein
- said fetch addresses are virtual memory addresses and said apparatus is switchable between a plurality of contexts sharing a common virtual address space such that an entry stored in said branch target buffer indicating a fetch address of a block of program instruction including a branch instruction in one context does not predict whether or not said fetch address corresponds to a block of program instructions containing said branch instruction when said apparatus is switched to a different context;
- and
- said branch target buffer entries are maintained across a context switch such that a hit within said branch target buffer following said context switch can be a false hit incorrectly predicting a branch instruction within a fetched block of program instructions and incorrectly resulting in a redirection of program flow;
- said apparatus further comprising:
- a false hit detecting circuit operable subsequent to said false hit incorrectly redirecting program flow to detect a false hit program instruction incorrectly predicted to be a taken branch instruction by said false hit and to invalidate an entry within said branch target buffer corresponding to said false hit.
7 more elements
A method of processing data under control of program instructions of variable length, said method comprising:
- storing said program instructions in a memory;
- fetching blocks of program instructions to be added to a sequence of program instructions to be decoded from fetch addresses within said memory;
- and
- storing in a branch target buffer a plurality of entries predicting fetch addresses of respective blocks of program instructions as containing a branch instruction to a branch target address, said branch target buffer being responsive to a fetch address of a block of program instructions being fetched from said memory by said fetch unit to detect a hit for an entry within said branch target buffer predicting that a branch instruction is present within said block of program instructions;
- wherein
- said fetch addresses are virtual memory addresses and said method of processing data is switchable between a plurality of contexts sharing a common virtual address space such that an entry stored in said branch target buffer indicating a fetch address of a block of program instruction including a branch instruction in one context does not predict whether or not said fetch address corresponds to a block of program instructions containing said branch instruction when said apparatus is switched to a different context;
- and
- said branch target buffer entries are maintained across a context switch such that a hit within said branch target buffer following said context switch can be a false hit incorrectly predicting a branch instruction within a fetched block of program instructions and incorrectly resulting in a redirection of program flow;
- said method further comprising:
- subsequent to said false hit incorrectly redirecting program flow, detecting with a false hit detecting circuit a false hit program instruction incorrectly predicted to be a branch instruction by said false hit and to invalidate an entry within said branch target buffer corresponding to said false hit.
7 more elements
Apparatus for processing data under control of program instructions of variable length, said apparatus comprising:
- memory means for storing said program instructions;
- a fetch unit means for fetching blocks of program instructions to be added to a sequence of program instructions to be decoded from fetch addresses within said memory means;
- and
- branch target buffer means for storing a plurality of entries predicting fetch addresses of respective blocks of program instructions as containing a branch instruction to a branch target address, said branch target buffer means being responsive to a fetch address of a block of program instructions being fetched from said memory means by said fetch unit means to detect a hit for an entry within said branch target buffer means predicting that a branch instruction is present within said block of program instructions;
- wherein
- said fetch addresses are virtual memory addresses and said apparatus is switchable between a plurality of contexts sharing a common virtual address space such that an entry stored in said branch target buffer means indicating a fetch address of a block of program instruction including a branch instruction in one context does not predict whether or not said fetch address corresponds to a block of program instructions containing said branch instruction when said apparatus is switched to a different context;
- and
- said branch target buffer entries are maintained across a context switch such that a hit within said branch target buffer means following said context switch can be a false hit incorrectly predicting a branch instruction within a fetched block of program instructions and incorrectly resulting in a redirection of program flow;
- said apparatus further comprising:
- a false hit detecting circuit means for, subsequent to said false hit incorrectly redirecting program flow, detecting a false hit program instruction incorrectly predicted to be a branch instruction by said false hit and to invalidate an entry within said branch target buffer means corresponding to said false hit.
7 more elements
Dependencies are inferred from the claim text.