Dynamically reconfigurable processor

A method of dynamically reconfiguring processing circuitry, the method comprising:

• receiving a plurality of program instructions to be executed by the processing circuitry, the program instructions comprising at least first and second instruction sets;
• configuring a reconfigurable logic circuit in a first data path when operating on data according to the first instruction set;
• and
• configuring the reconfigurable logic circuit in a second data path when operating on data according to the second instruction set.

A custom LSI development platform for the development of structure and circuitry, the platform comprising:

• an instruction set generator for generating instruction sets for a processor, the instructions comprising instructions from at least first and second instruction sets;
• a compiler for generating instructions according to the generated instruction sets;
• and
• a logic circuit configuration generator that generates logic circuit configuration information for first and second data paths within a dynamically reconfigurable logic circuit, wherein the first and second data paths provide circuitry that are operable for execution of the generated instructions from the respective first and second instruction sets.

A method for generating an instruction set architecture of a processor, the method comprising:

• extracting an instruction pattern from an instruction in a program described in a high-level language;
• comparing the extracted instruction pattern with patterns of one or more custom instructions stored in a library;
• and
• substituting the instruction in the program with the one or more custom instructions to generate the instruction set architecture.

A method for generating logic circuit configuration information for a processor, the method comprising:

• extracting an instruction pattern from an instruction in a program described in a high-level language;
• comparing the extracted instruction pattern with patterns of one or more custom instructions;
• substituting the instruction in the program with the one or more custom instructions;
• and
• generating the logic circuit configuration information from logic element connection information associated with the one or more custom instructions and from layout arrangement information of at least one programmable element of the processor.

A dynamic logic circuit reconfigurable processor, comprising:

• a dynamically reconfigurable logic circuit comprising at least one programmable element;
• a configuration memory that stores layout arrangement information for each instruction of the at least one programmable element;
• a register file that temporarily holds a middle result of executing the instructions of the at least one programmable element;
• a memory that holds the instructions;
• and
• a controller that manages the processor, the controller managing an executing order of the instructions of the at least one programmable element.

A custom LSI development platform, comprising:

• a dynamic logic circuit reconfigurable processor having at least one programmable element comprising the logic circuit;
• and
• a software module, the software module comprising:
• an instruction set architecture generator for generating an instruction set architecture of the processor, and
• a logic circuit configuration generator that generates logic circuit configuration information of the processor from layout arrangement information of the at least one programmable element and the instruction set architecture.

A computer-readable medium containing a set of instructions to be executed in a computer for generating an instruction set architecture of a dynamic logic circuit reconfigurable processor, the set of instructions comprising:

• extracting an instruction pattern from an instruction in an application program of the processor described in a high-level language;
• comparing the extracted instruction pattern with patterns of one or more custom instructions stored in a library;
• and
• substituting the instruction in the program with the one or more custom instructions to generate the instruction set.

A computer-readable medium containing a set of instructions to be executed in a computer for generating logic circuit configuration information for a dynamic logic circuit reconfigurable processor, the set of instructions comprising:

• extracting an instruction pattern from an instruction in a program described in a high-level language;
• comparing the extracted instruction pattern with patterns of one or more custom instructions;
• substituting the instruction in the program with the one or more custom instructions to generate an instruction set;
• and
• generating the logic circuit configuration information from logic element connection information associated with the one or more custom instructions included in the instruction set and from layout arrangement information of at least one programmable element of the processor.