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US 2006/0242364 A1Published application
Semiconductor storage device and cache memory
AssigneeNEC Electronics Corporation
InventorSatoshi Chiba
Life of this patent
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Abstract
A semiconductor storage device according to an embodiment of the present invention includes: a first latch circuit for latching stored data; and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit, and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.
Claims9
A semiconductor storage device, comprising:
- a first latch circuit for latching stored data;
- and
- a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit, and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.
A semiconductor storage device, comprising:
- a first latch circuit for latching writing data;
- and
- a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit, and receives the writing data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.
A cache memory including a semiconductor storage device, comprising:
- a data memory;
- a first memory for storing tag data;
- a second memory for storing data about whether or not data in the data memory is valid;
- a third memory for storing data about whether or not the data in the data memory is changed,
- the first, second, and third memories being provided in the semiconductor storage device and at least one of the first, second, and third memories including:
- a first latch circuit for latching stored data to be stored in the at least one of the first, second, and third memories;
- and
- a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit, and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.
5 more elements
Dependencies are inferred from the claim text.