Core logic device of computer system

Abstract

A core logic device is provided to a computer system having a central processing unit (CPU) and a peripheral device. The core logic device includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by the peripheral device before an operating system is loaded in the computer system. Accordingly, the virtual wire unit outputs an interrupt control packet to the CPU wherein the interrupt vector contents carried by the interrupt control packet is ignored by the CPU. Alternatively, after the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal. Hence, the code enabling the CPU to read interrupt vector information can be transmitted to the CPU and will not be cleared while the I/O APIC is initialized by a specific operating system.

Dependencies are inferred from the claim text.