Power-efficient encoder architecture for data stream on bus and encoding method thereof

Abstract

The present invention discloses a power-efficient encoder architecture for address stream on bus and a power-efficient encoding method for address stream on bus. In the design of the encoder architecture, a encoder is installed on the path along which the address stream flows from the central processing unit to a bus, and another encoder is installed on the path along which the address stream flows from the bus to a memory, and the aforementioned encoders all have the encode/decode function. In the design of the encoding method, each address stream is equipped with a corresponding stride, wherein the strides of different address streams are not necessarily the same; the related stride can be used to predict hit stride and help calculating the address where the next data stream will appear; the stride of each address stream can be dynamically modified, and the transferred contents for the address stream corresponds to the portion that enables the bus capacitors to switch less times; the maximum switching number of the bus capacitors is reduced to two to the K-th power. Via the encoding of the present invention, the switching number of the bus capacitors can be reduced to the least with the same transmission frequency, and thus the objective of reducing the power consumption of the bus is achieved.

Dependencies are inferred from the claim text.