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US 2006/0242255 A1Published application
High-speed data readable information processing device
AssigneeRenesas Technology Corp.
InventorsHideo Inoue, Isao Minematsu, Takahiro Ikenobe
Life of this patent
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Abstract
A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
Claims7
An information processing device, comprising:
- a main storage memory;
- a CPU for system;
- a high-speed system bus connected to said main storage memory and said CPU;
- a message box for receiving and temporarily storing at least one message;
- a memory access control circuit operable independently of said CPU and accessible to said main storage memory for transferring a message received at said message box;
- and
- a low-speed bus which is connected to said message box and on which said message is transmitted, wherein
- said message box outputs a message reception request when receiving said message, and
- said memory access control circuit accesses said message box and said main storage memory to transfer a message received in response to said message reception request which is stored in said message box to said main storage memory.
6 more elements
Dependencies are inferred from the claim text.