Test apparatus and program therefor

A program for operating a test apparatus for testing DUTs as:

• a plurality of test modules for supplying test patterns used in testing said DUTs to said DUTs corresponding to a given timing signal;
• a reference clock generating section for generating a reference clock;
• a plurality of timing supply sections, provided corresponding to said plurality of test modules, for generating the timing signal corresponding to the reference clock and supplying the timing signal to said corresponding test module, respectively;
• and
• a control section for controlling timing for outputting the timing signals output by said timing supply sections so that timing of said respective test patterns output by said plurality of test modules is practically equalized based on a test module delay of each test module until when it outputs the test pattern after receiving the timing signal.

A test apparatus for testing DUTs, comprising:

• a plurality of test modules for supplying test patterns used in testing said DUT to said DUT corresponding to a given timing signal and for generating a fail timing signal specifying whether or not said DUT is non-defective based on an output signal of said DUT;
• a reference clock generating section for generating a reference clock;
• a plurality of timing supply sections, provided corresponding to said plurality of test modules, for generating the timing signal corresponding to the reference clock and supplying the timing signal to said corresponding test module, respectively;
• a plurality of return system circuits, provided in correspondence to said plurality of test modules, for receiving said fail timing signal output by said corresponding test module, delaying and inputting the fail timing signal to said timing supply section and generating the timing signal corresponding to the fail timing signal;
• and
• a control section for controlling timing of each of said return system circuit in outputting said fail timing signal so that timing when each fail timing signal output by said plurality of test modules is inputted to said timing supply section is practically equalized based on the test module delay of each test module until when it outputs the fail timing signal to said return system circuit after generating the fail timing signal.

A program for operating a test apparatus for testing DUTs as:

• a plurality of test modules for supplying test patterns used in testing said DUT to said DUT corresponding to a given timing signal and for generating a fail timing signal specifying whether or not said DUT is non-defective based on an output signal of said DUT;
• a reference clock generating section for generating a reference clock;
• a plurality of timing supply sections, provided corresponding to said plurality of test modules, for generating the timing signal corresponding to the reference clock and supplying the timing signal to said corresponding test module, respectively;
• a plurality of return system circuits, provided in correspondence to said plurality of test modules, for receiving the fail timing signal output by said corresponding test module, delaying and inputting the fail timing signal to said timing supply section and generating the timing signal corresponding to the fail timing signal;
• and
• a control section for controlling timing of each of said return system circuit in outputting the fail timing signal so that timing when each fail timing signal output by said plurality of test modules is inputted to said timing supply section is practically equalized based on the test module delay of each test module until when it outputs the fail timing signal to said return system circuit after generating the fail timing signal.