Semiconductor integrated circuit and method of testing delay thereof

A method of delay testing a semiconductor integrated circuit, applied to a semiconductor integrated circuit including a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency;

• and a second area, formed on the semiconductor chip, which operates at a second voltage and a second frequency lower than the first voltage and the first frequency, respectively, and also operates after a shift to the first voltage and the first frequency;
• the method comprising:
• providing a third area, formed on the semiconductor chip, which operates at the first voltage and a frequency which operates the second area and transmits and receives signals sent between the first area and the second area;
• providing beforehand, within the third area, a delay analysis endpoint that can analyze each of a first delay occurring between the first area and the third area and a second delay occurring between the second area and the third area;
• and
• testing a delay of the semiconductor chip by detecting the first delay and the second delay with the delay analysis endpoint.