Apparatus to improve bandwidth for circuits having multiple memory controllers

A system for improving bandwidth among a plurality of memory controllers, said system comprising:

• a first memory controller electrically communicating with an external data and address bus for controlling a first memory circuit;
• a second memory controller electrically communicating with an external data and address bus for controlling a second memory circuit;
• a first output signal circuit electrically communicating with the first memory controller, wherein said first output signal has means for signaling when the said first memory controller releases said address bus for a next external access subsequent to an access to said data bus by said first memory controller;
• a second output signal circuit electrically communicating with the first memory controller, wherein said second output has mean for signaling when the said first memory controller releases said data bus for a next external subsequent to an access to said data bus by said first memory controller;
• a first output signal circuit electrically communicating with the second memory controller, wherein said first output signal has means for signaling when the said second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller;
• and
• a second output signal circuit electrically communicating with the second memory controller, wherein said second output has means for signaling when the said second memory controller releases said data bus for a next external access subsequent to an access to said data bus by said second memory controller.

The method of improving bandwidth for circuits having a plurality of memory controllers, said method comprising the steps of:

• a) asserting a first output signal to indicate when a first memory controller releases an address bus for a next external access subsequent to an access to said data bus by said first memory controller;
• b) asserting a second output signal to indicate when said first memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said first memory controller;
• c) asserting a first output signal to indicate when a second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller;
• and
• d) asserting a second output signal to indicate when said second memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said second memory controller.