Direct memory access controller

A system LSI including a direct memory access controller, comprising

• a direct memory access controller arranged and configured to execute data transfer control when data transfers are made;
• a CPU arranged and configured to execute various commands and instruct the direct memory access controller to execute data transfers;
• a plurality of devices arranged and configured to store various data;
• and
• a bus for transferring data between devices that are connected thereto,
• the direct memory access controller comprising:
• an internal register arranged and configured to receive and store transfer information related to transfer data to be transferred, said transfer information including a data transfer origin address, a data transfer destination address, and information related to size of the transfer data;
• a transfer control unit arranged and configured to issue a transfer command, said transfer command for acquiring the transfer data from a device associated with the data transfer origin address via the bus based on the data transfer origin address and size of the transfer data stored in the internal register and sending the transfer data to a device associated with the data transfer destination address via the bus;
• a buffer arranged and configured to store the transfer data acquired in response to the transfer control unit;
• and
• an interface arranged and configured to receive the transfer data from the device associated with the data transfer origin address based on the received transfer command, the interface arranged and configured to send the received transfer data to the device associated with the transfer destination address,
• wherein the transfer control unit issues commands such that the transfer data is divided into portions each having a prescribed transfer unit size and the portions of transfer data are sent separately to the device associated with the transfer destination address in such a manner that the final portion of the transfer data is transferred using a transfer method that requires a response from the device associated with the data transfer destination address and all other portions of the transfer data are transferred using a transfer method that does not require a response from the device associated with the data transfer destination, and the transfer control notifies the CPU that the transfer is complete when said response is received.

A data transfer method employing a direct memory access controller, comprising:

• receiving transfer information related to a transfer data, said transfer information including a data transfer origin address, a data transfer destination address, and information related to the size of the data to be transferred;
• storing the transfer information;
• acquiring a portion of the transfer data, based the data transfer origin address and size of the transfer data, from a device associated with the data transfer origin address, said portion of the transfer data having a prescribed transfer unit size;
• storing acquired portion of transfer data;
• determining whether or not said portion of transfer data is the final portion of transfer data;
• and
• if said portion of transfer data is not the final portion of transfer data, transferring the portion of the transfer data to a device associated with the data transfer destination address using a transfer method that does not require a response from the device associated with the data transfer destination address,
• if said portion of transfer data is the final portion of transfer data, transferring the portion of the transfer data to a device associated with the data transfer destination address using a transfer method that requires a response from the device associated with the data transfer destination address.