Method and system of split-streaming direct memory access
OwnerJohn Falkowski, Bruce Littlefield +2inventors
InventorsJohn Falkowski, Bruce Littlefield, Hussein Mecklai, Stanley Reinhold
Life of this patent
Estimating the term…
Abstract
A method and system of split-streaming direct memory access (DMA) data transfer can transfer N words of data from a source device to two different sets of memory locations using only N data read cycles and 2N data write cycles. In a single data word transfer mode, a data read operation on the memory bus is followed by two consecutive data write cycles wherein the same data is written to two different memory addresses. In a data burst mode, a data burst read operation is followed by a series of paired data write cycles, wherein in each pair of data write cycles, one of the data words is written to two different memory addresses.
Claims21
A method of transferring data, comprising:
- executing a direct memory access (DMA) read operation on a memory bus to read data from a source device during a DMA read cycle;
- executing a first DMA write operation on the memory bus to write the data to a first memory location identified by a first memory address, during a first DMA write cycle;
- and
- executing a second DMA write operation on the memory bus to write the data to a second memory location identified by a second memory address, during a second DMA write cycle immediately subsequent to the first DMA write cycle.
A method of transferring data, comprising:
- executing a direct memory access (DMA) read operation on a memory bus to read a plurality of data from a source device into a register set associated with a DMA controller connected to the memory bus;
- and
- executing a DMA write operation on the memory bus to write the plurality of data from the register set to a first plurality of memory locations associated with a first set of memory addresses, and to a second plurality of memory locations associated with a second set of memory addresses.
A data processing system, comprising:
- a memory bus for communicating data, the memory bus including a plurality of data lines and a plurality of address lines;
- and
- a direct memory access (DMA) memory controller connected to the data bus and adapted to take control of the memory bus to execute a DMA read operation on the memory bus to read data on the data bus, to execute a first DMA write operation on the memory bus to write the data to a first memory location associated with a first memory address during a first DMA write cycle, and to execute a second DMA write operation on the memory bus to write the data to a second memory location associated with a second memory address during a second DMA write cycle immediately subsequent to the first DMA write cycle.
A data processing system, comprising:
- a memory bus for communicating data, the memory bus including a plurality of data lines and a plurality of address lines;
- and
- a direct memory access (DMA) memory controller connected to the data bus and adapted to take control of the memory bus to execute a DMA read operation on the memory bus to read data on the data bus, to execute a first DMA write operation on the memory bus to write the data to a first plurality of memory locations associated with a first set of memory addresses during a first plurality of consecutive DMA write cycles, and to execute a second DMA write operation on the memory bus to write the data to a second plurality of memory locations associated with a second plurality of memory addresses during a second plurality of consecutive DMA write cycles, where the second plurality of consecutive second DMA write cycles is immediately subsequent to the first plurality of consecutive DMA write cycles.
Dependencies are inferred from the claim text.