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US 2006/0235923 A1Published application
Carry-ripple adder
AssigneeInfineon Technologies AG
InventorsJoel Hatsch, Winfried Kamp
Life of this patent
Estimating the term…
Abstract
A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2 w.
Claims24
A carry-ripple adder, comprising:
- four summing inputs for receiving four input bits having the significance w that are to be summed;
- three carry inputs for receiving three input carry bits having the significance w;
- a summation output for outputting an output summation bit having the significance w;
- and
- three carry outputs for outputting three output carry bits having the significance 2 w.
2 more elements
An adding device for summing a plurality of bit sets each comprising bits having the same significance w;
- wherein
- bits of different of said bit sets have a different significance;
- a carry-save adder is assigned to each of said bit sets;
- a respective of said carry-save adders summing the bits of a respective of said bit set and outputting an intermediate summation bit having the significance w of said respective bit set and outputting at least two intermediate carry bits having the respective next higher significance 2 w;
- and
- a carry-ripple adder is assigned to at least one of said bit sets;
- said carry-ripple adder summing the respective of said intermediate summation bits having the significance w and at least two of said intermediate carry bits having the significance w of said respective bit set having the next lower significance w/2 taking account of at least two of said carry bits having the significance w, which were obtained during said summation of said bit sets having a lower significance, as input carry bits and for outputting a bit set summation bit having the significance w of said respective bit set and at least two of said carry bits having the respective next higher significance 2 w as output carry bits.
4 more elements
Dependencies are inferred from the claim text.