Method and apparatus for providing packed shift operations in a processor

A system comprising:

• a memory to hold a plurality of data elements;
• a processor comprising:
• a decoder operable to decode a first instruction of a packed data instruction set, said instruction operable to specify a shift operation to be performed on a first packed data sequence having a plurality of packed data elements, said first instruction further operable to specify a variable size of the data elements included in said packed data sequence, and
• a circuit coupled to said decoder, said circuit operable to shift said plurality of packed data elements independently, in response to said first instruction;
• a bus coupled with the processor to transmit data to and from the processor and to and from the memory;
• and
• an interface to couple the bus with one or more devices to provide data to or receive data from the bus, said one or more devices comprising an audio device selected from the group consisting of an audio digitizing device, a sound recording device, a sound playback device, a microphone, a digital-to-analog converter, and a speaker.