Competitive circuit price model and method

A method of calculating a competitive base wafer cost for use in a model for calculating a packaged integrated circuit (IC) cost for a first integrated circuit of a first IC technology, the method comprising:

• (a) determining a base wafer price for a first wafer technology at a desired time of analysis;
• and
• (b) applying a competitive wafer gross margin for said desired time of analysis to said base wafer price to determine the competitive base wafer cost, said competitive wafer gross margin based on information obtained by:
• (i) determining a second wafer technology at the statistical mode of a wafer distribution for a first foundry for an available date;
• (ii) determining a first amount of time from an initial date of production of said second wafer technology to said available date;
• (iii) plotting a function using a first point at an initial time of a gross margin versus time plot, a second point at a terminal time of said gross margin versus time plot, and a third point at said first amount of time from said initial time of said gross margin versus time plot, said first point corresponding to an industry maximum attainable wafer gross margin, said second point corresponding to an industry minimum attainable wafer gross margin, said third point corresponding to an industry available gross margin for said first foundry for said available date;
• and
• (iv) assigning a value from said function as said competitive wafer gross margin.