Method for fabricating an integrated circuit comprising a three-dimensional capacitor

An integrated circuit comprising at least one capacitor extending within a dielectric material, comprising:

• a metal layer embedded in the dielectric material;
• at least two capacitive trenches whose bottoms bear on the metal layer;
• and
• a layer of conductive material forming a lower electrode of the capacitor which lies at least on the sidewalls of the trenches and is in contact with the metal layer;
• wherein the capacitor extends over at least two interconnection levels of the integrated circuit, and the embedded metal layer forms part of the metallization level of a lower interconnection level, further comprising a contact terminal bearing directly on the lower electrode, to an upper interconnection level lying above the lower interconnection level, within the dielectric material.

An integrated circuit, comprising:

• a buried metallization layer;
• dielectric material overlying the buried metallization layer;
• at least two trenches formed in the dielectric material extending down to expose the buried metallization layer;
• a first conductive material layer forming a lower electrode of a capacitor on the sides of the at least two trenches and the exposed buried metallization layer;
• a dielectric layer covering the first conductive material layer within at least the at least two trenches;
• a second conductive material layer forming an upper electrode of the capacitor covering the dielectric layer within at least the at least two trenches
• wherein the capacitor extends over at least two interconnection levels of the integrated circuit, and the buried metallization layer forms part of the metallization level of a lower interconnection level, further comprising a contact terminal directly in contact with the lower electrode at an upper interconnection level lying above the lower interconnection level.

A method, comprising:

• forming a metallization layer buried within an overlying dielectric material;
• forming at least two trenches the dielectric material extending down to expose the buried metallization layer;
• depositing a first conductive material layer forming a lower electrode of a capacitor on the sides of the at least two trenches and the exposed buried metallization layer;
• depositing a dielectric layer covering the first conductive material layer within at least the at least two trenches;
• depositing a second conductive material layer forming an upper electrode of the capacitor covering the dielectric layer within at least the at least two trenches;
• wherein the capacitor extends over at least two interconnection levels of the integrated circuit, and the buried metallization layer forms part of the metallization level of a lower interconnection level, further comprising making direct electrical terminal contact with the lower electrode at an upper interconnection level lying above the lower interconnection level.