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US 2006/0234456 A1Published application
Four-bit finfet nvram memory device
AssigneeInternational Business Machines Corporation
InventorsBrent Anderson, William Clark, Edward Nowak
Life of this patent
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Abstract
A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.
Claims23
A method of fabricating a semiconductor device, comprising:
- providing a silicon layer on top surface of an insulation layer of a substrate;
- forming a fin body from said silicon layer, said fin body having opposite first and second ends and opposite first and second sidewalls, said first and second sidewalls disposed between said first and second ends;
- forming a first gate dielectric stack on said first sidewall and a second gate dielectric stack on said second sidewall, said first and second stacks each comprising at least a first, a second and a third dielectric layer, said first dielectric layer of said first dielectric stack in direct physical contact with said first sidewall and said first dielectric layer of said second dielectric stack in direct physical contact with said second sidewall;
- forming a first gate electrode in direct physical contact with said third dielectric layer of said first gate dielectric stack and a second gate electrode in direct physical contact with said third dielectric layer of said second gate dielectric stack, said first and second gate electrodes not in direct physical contact with each other;
- and
- forming a first source/drain in said first end of said fin body and a second source/drain in said second end of said fin body, said first and second source/drain regions separated by a channel region in said fin body, said channel region aligned between said first and second gate electrodes.
3 more elements
A method, comprising:
- forming a fin body in silicon layer on a top surface of an insulation layer of a substrate, said fin body having opposite first and second ends and opposite first and second sidewalls, said first and second sidewalls disposed between said first and second ends;
- forming a first gate dielectric stack disposed on said first sidewall and forming a second gate dielectric stack disposed on said second sidewall, said first and second stacks each comprising at least a first, a second and a third dielectric layer, said first dielectric layer of said first dielectric stack in direct physical contact with said first sidewall and said first dielectric layer of said second dielectric stack in direct physical contact with said second sidewall;
- forming a first gate electrode in direct physical contact with said third dielectric layer of said first gate dielectric stack and forming a second gate electrode in direct physical contact with said third dielectric layer of said second gate dielectric stack, said first and second gate electrodes not in direct physical contact with each other;
- forming a first source/drain in said first end of said fin body and forming a second source/drain in said second end of said fin body;
- and
- forming a channel region in said fin body between said first and second source/drains and aligned between said first and second gate electrodes.
3 more elements
Dependencies are inferred from the claim text.