Alignment mark and alignment method for the fabrication of trench-capacitor dram devices

A method of fabricating a microelectronic device, comprising:

• providing a semiconductor substrate having thereon a device region and an alignment mark region;
• simultaneously etching capacitor trenches into the semiconductor substrate within the device region, and forming alignment mark within the alignment mark region, wherein the alignment mark comprises a plurality of trench lines, and each of the trench lines has a width of smaller than 0.5 microns;
• fabricating a trench capacitor within each of the capacitor trenches at least comprising depositing polysilicon layer into the capacitor trenches and simultaneously into the trench lines;
• forming a first photoresist layer over the semiconductor substrate, the first photoresist layer having an opening that merely exposing the alignment mark region and the alignment mark;
• performing a first etching process to etch the polysilicon layer within the exposed trench lines of the alignment mark;
• stripping the first photoresist layer;
• forming a second photoresist layer over the semiconductor substrate;
• performing a wafer alignment process comprising irradiating the alignment mark using an alignment light beam that passes through the second photoresist layer, thereby acquiring wafer alignment information;
• and
• performing an exposure process employing a photomask defining avtive area pattern thereon, thereby transferring the avtive area pattern to the second photoresist layer.