Maskless multiple sheet polysilicon resistor

A method of forming a polysilicon resistor device having a low temperature coefficient of resistivity comprising:

• forming an insulative layer over a semiconductor substrate;
• forming a polysilicon layer on the insulative layer;
• forming a first resistor mask having a first exposure pattern on the polysilicon layer;
• implanting a first dopant into the polysilicon layer through the first exposure pattern;
• performing a first thermal activation process that diffuses the implanted first dopant to a substantially uniform concentration in the polysilicon layer;
• removing the first resistor mask;
• forming a second resistor mask having a second exposure pattern on the polysilicon layer
• implanting a second dopant of opposite conductivity type to the first dopant into the polysilicon layer through the second exposure pattern;
• performing a second thermal activation process that diffuses the implanted second dopant to a substantially uniform concentration in the polysilicon layer;
• and
• removing the second resistor mask.

A method of forming a polysilicon resistor device comprising:

• forming an insulative layer over a semiconductor substrate;
• forming a polysilicon layer on the insulative layer;
• defining a plurality of polysilicon resistors within the polysilicon layer;
• forming a resistor mask having a plurality of exposure patterns on the polysilicon layer, wherein the plurality of exposure patterns are associated with and formed over the plurality of polysilicon resistors;
• implanting a selected dopant into the polysilicon layer through the exposure patterns;
• and
• performing a thermal activation process that diffuses the implanted dopant in the polysilicon layer.

A method of fabricating a semiconductor device having polysilicon resistors comprising:

• performing well formation and isolation processing in a semiconductor body in NMOS and PMOS regions;
• forming a gate dielectric layer on the semiconductor body;
• forming a polysilicon layer on the gate dielectric layer;
• patterning the polysilicon layer to form polysilicon gates in the NMOS and PMOS regions and polysilicon resistors in a resistor region;
• forming extension regions in active areas in the NMOS and PMOS regions;
• forming sidewall spacers adjacent the offset spacers;
• forming an NMOS source/drain and resistor mask that covers the PMOS region and exposes the NMOS region and partially exposes polysilicon resistors within the resistor region;
• implanting n-type dopant(s) to form source/drain regions in the NMOS region and adjust resistivity of the polysilicon resistors;
• removing the NMOS source/drain and resistor mask;
• forming a PMOS source/drain and resistor mask that covers the NMOS region and exposes the PMOS region;
• implanting p-type dopant(s) to form source/drain regions in the PMOS region;
• and
• removing the PMOS source/drain and resistor mask.