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US 2006/0234432 A1Published application
SOI bottom pre-doping merged e-SiGe for poly height reduction
AssigneeToshiba America Electronic Components, Inc.
InventorYusuke Kohyama
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Abstract
Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor
Claims14
A method for forming a semiconductor device, comprising:
- forming a transistor gate on a silicon body;
- forming recessed portions of the silicon body on opposing sides of the gate;
- performing first doping of the recessed portions;
- forming an SiGe layer on the recessed portions after the step of performing first doping;
- and
- performing second doping of the gate after the SiGe layer is formed.
3 more elements
A semiconductor device comprising:
- a silicon-on-insulator wafer including a silicon body disposed over a buried oxide layer;
- and
- a transistor, including:
- a transistor gate disposed on the silicon body between the recesses,
- a pair of source/drain regions, and
- a channel region in the silicon body,
- wherein the source/drain regions are doped with boron ions so as to each abut the buried oxide layer, and wherein the channel region is not penetrated with boron ions.
4 more elements
Dependencies are inferred from the claim text.