Technique for compensating for substrate shrinkage during manufacture of an electronic assembly

An electronic assembly with substrate shrinkage compensation, comprising:

• a substrate having a horizontal line having a plurality of vertical graduations across a horizontal portion of a substrate and vertical line having a plurality of horizontal graduations across a vertical portion of the substrate, wherein the substrate includes a plurality of solder pads formed on at least one surface of the substrate;
• and
• a plurality of electronic components coupled to one or more of the solder pads, wherein an amount of substrate shrinkage is determined based upon a location change in the graduations of the horizontal and vertical lines and a solder that electrically connects the electronic components to the solder pads is deposited on the solder pads responsive to the amount of substrate shrinkage.