Method for predicting and optimizing chip performance in cured thermoset coatings

A nested transimpedance amplifier (TIA) circuit, comprising:

• a zero-order TIA having an input and an output;
• a first operational amplifier (opamp) having an input that communicates with said output of said zero-order TIA and an output;
• a first feedback resistance having one end that communicates with said input of said zero-order TIA and an opposite end that communicates with said output of said first opamp;
• a second feedback resistance having a first end that communicates with said input of said first opamp and an opposite end that communicates with said output of said first op-amp;
• a first feedback capacitance having a first end that communicates with said input of said zero-order TIA and a second end that communicates with said output of said zero-order TIA.

A nested transimpedance amplifier (TIA) circuit, comprising:

• a zero-order TIA having an input and an output;
• a first operational amplifier (opamp) having an input that communicates with said output of said zero-order TIA and an output;
• a first feedback resistance having one end that communicates with said input of said zero-order TIA and an opposite end that communicates with said output of said first opamp;
• and
• a second feedback resistance having a first end that communicates with said input of said first opamp and an opposite end that communicates with said output of said first op-amp, wherein said first opamp includes metal-oxide-semiconductor transistors and a bandwidth of said nested TIA circuit is greater than 10% of a threshold frequency.

A nested differential mode TIA circuit, comprising:

• a zero-order differential mode TIA having first and second inputs and first and second outputs;
• a first differential mode opamp having first and second inputs that communicate with said first and second outputs of said zero-order differential mode TIA and first and second outputs;
• a first feedback resistance having one end that communicates with said first input of said zero-order differential mode TIA and an opposite end that communicates with said first output of said first differential mode opamp;
• a second feedback resistance having one end that communicates with said second input of said zero-order differential mode TIA and an opposite end that communicates with said second output of said first differential mode opamp;
• third feedback resistance having a first end that communicates with said first input of said first differential mode opamp and an opposite end that communicates with said first output of said first differential mode op-amp;
• and
• fourth feedback resistance having a first end that communicates with said second input of said first differential mode opamp and an opposite end that communicates with said second output of said first differential mode op-amp, wherein said zero order differential mode TIA includes a second differential mode opamp and a third differential mode opamp having first and second inputs that communicates with first and second outputs of said second differential mode opamp and first and second outputs.

A nested differential mode TIA circuit, comprising:

• a zero-order differential mode TIA having first and second inputs and first and second outputs;
• a first differential mode opamp having first and second inputs that communicate with said first and second outputs of said zero-order differential mode TIA and first and second outputs;
• a first feedback resistance having one end that communicates with said first input of said zero-order differential mode TIA and an opposite end that communicates with said first output of said first differential mode opamp;
• a second feedback resistance having one end that communicates with said second input of said zero-order differential mode TIA and an opposite end that communicates with said second output of said first differential mode opamp;
• third feedback resistance having a first end that communicates with said first input of said first differential mode opamp and an opposite end that communicates with said first output of said first differential mode op-amp;
• fourth feedback resistance having a first end that communicates with said second input of said first differential mode opamp and an opposite end that communicates with said second output of said first differential mode op-amp;
• a first capacitance having a first end that communicates with said first input of said zero-order differential mode TIA and a second end that communicates with said first output of said zero-order differential mode TIA;
• and
• a second capacitance having a first end that communicates with said second input of said zero-order differential mode TIA and a second end that communicates with said second output of said zero-order differential mode TIA.

A nested differential mode TIA circuit, comprising:

• a zero-order differential mode TIA having first and second inputs and first and second outputs;
• a first differential mode opamp having first and second inputs that communicate with said first and second outputs of said zero-order differential mode TIA and first and second outputs;
• a first feedback resistance having one end that communicates with said first input of said zero-order differential mode TIA and an opposite end that communicates with said first output of said first differential mode opamp;
• a second feedback resistance having one end that communicates with said second input of said zero-order differential mode TIA and an opposite end that communicates with said second output of said first differential mode opamp;
• third feedback resistance having a first end that communicates with said first input of said first differential mode opamp and an opposite end that communicates with said first output of said first differential mode op-amp;
• and
• fourth feedback resistance having a first end that communicates with said second input of said first differential mode opamp and an opposite end that communicates with said second output of said first differential mode op-amp, wherein said zero order differential mode TIA includes a second differential mode opamp having first and second inputs and first and second outputs.

A nested transimpedance amplifier (TIA) circuit, comprising:

• a zero-order TIA having an input and an output;
• a first operational amplifier (opamp) having an input that communicates with said output of said zero-order TIA and an output;
• a first feedback resistance having one end that communicates with said input of said zero-order TIA and an opposite end that is directly connected to said output of said first opamp;
• and
• a second feedback resistance having a first end that communicates with said input of said first opamp and an opposite end that communicates with said output of said first op-amp.

A nested differential mode TIA circuit, comprising:

• a zero-order differential mode TIA having first and second inputs and first and second outputs;
• a first differential mode opamp having first and second inputs that communicates with said first and second outputs of said zero-order differential mode TIA and first and second outputs;
• a first feedback resistance having one end that communicates with said first input of said zero-order differential mode TIA and an opposite end that is directly connected to said first output of said first differential mode opamp;
• a second feedback resistance having one end that communicates with said second input of said zero-order differential mode TIA and an opposite end that is directly connected to said second output of said first differential mode opamp;
• third feedback resistance having a first end that communicates with said first input of said first differential mode opamp and an opposite end that communicates with said first output of said first differential mode op-amp;
• and
• fourth feedback resistance having a first end that communicates with said second input of said first differential mode opamp and an opposite end that communicates with said second output of said first differential mode op-amp.