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US 2006/0234403 A1Published application
WAT process to avoid wiring defects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLin-Ping Li, Yung-Cheng Lu, Wen-Chih Chiou, Chih-Hsien Lin
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Abstract
A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.
Claims19
A method for forming a multi-level semiconductor device comprising the steps of:
- forming a first metallization layer;
- performing a wafer acceptance testing (WAT) process;
- and,
- then performing a chemical mechanical polish (CMP) on the metallization layer.
1 more element
A method for forming a multi-level semiconductor device comprising the steps of:
- providing a dielectric layer with a dielectric constant less than 3.9;
- forming an opening in the dielectric layer;
- filling the opening with a conductor;
- probing the conductor according to a WAT test;
- and,
- then performing a CMP process on the conductor.
3 more elements
Dependencies are inferred from the claim text.