Method and apparatus for efficient multi-stage FIR filters
AssigneeTexas Instruments Incorporated
InventorSrikanth Gurrapu
Life of this patent
Estimating the term…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorSrikanth Gurrapu
Estimating the term…
An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.
A digital signal processing filter configured to alter the sampling rate of a sampled input signal and produce a filtered output signal, comprising:
A signal processing system configured with a digital signal processing filter that alters the sampling rate of a sampled input signal and produces a filtered output signal, comprising:
A method of altering the sampling rate of a sampled input signal to produce a filtered output signal comprising:
Dependencies are inferred from the claim text.