Multiple data rates in programmable logic device serial interface

A configurable serial interface receiver for use in a programmable logic device, said serial interface receiver comprising:

• a plurality of stages selected from the group consisting of a word alignment stage comprising at least one block providing word-aligned output, a de-skew stage comprising at least one block providing de-skewed output, a rate matching stage comprising at least one block providing rate-matched output, a padded protocol decoder stage comprising at least one block providing decoded output, a byte deserializer stage comprising at least one block providing deserialized output, a byte reorder stage comprising at least one block providing reordered output and a phase compensation stage comprising at least one block providing phase-compensated output;
• bypass circuitry around each said stage;
• and
• selector circuitry associated with each said stage for selecting, with respect to said stage, between output of said stage and said bypass circuitry around said stage;
• whereby:
• any one of said plurality of stages is programmably includable in said configurable serial interface receiver.