Controllable frequency divider circuit, transmitter/receiver with a controllable frequency divider circuit, and a method for carrying out a loop-back test
OwnerFrank Demmerleinventor
Life of this patent
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Abstract
A frequency divider circuit can be utilized for loop-back tests in a transmitter/receiver. In one embodiment, provision is made for a multiplexer to be connected downstream from a frequency divider, whose output side produces signal elements with different phases. The multiplexer is designed to periodically switch its inputs to its output by means of a control signal at its control input. The periodicity of the switching results in a frequency offset with respect to an unswitched signal, by which means a test signal is produced with a difference frequency during frequency conversion. Other systems and methods are also disclosed.
Claims20
A controllable frequency divider circuit, comprising:
- a signal input for supplying a clock signal;
- a signal output;
- a front-end flipflop circuit with a clock input that is coupled to the signal input, with a data input, with an un-inverted data output, and with a inverted data output;
- at least one intermediate flipflop circuit with a clock input that is coupled to the signal input, with a data input that is connected to the un-inverted data output of the front-end flipflop, with an un-inverted data output, and with an inverted data output that is coupled to the data input of the front-end flipflop circuit forming a feedback path;
- a multiplexer with a first signal input that is connected to the un-inverted data output of the front-end flipflop circuit, with a second signal input that is coupled to the un-inverted data output of the intermediate flipflop circuit, with a third signal input that is coupled to the inverted data output of the front-end flipflop circuit, and with a fourth signal input that is coupled to the inverted data output of the intermediate flipflop circuit, with a multiplexer data output, and with a multiplexer control input, and with the multiplexer being designed to periodically controllably pass one of the first, second, third, or fourth signal inputs to the multiplexer data output as a function of a frequency of a control signal that is supplied to the multiplexer control input.
A method for carrying out a loop-back test, comprising the following steps:
- provision of a transmission path;
- provision of a reception path with a frequency divider to which a local oscillator signal can be supplied;
- coupling of the transmission path to the reception path;
- production of a carrier signal at one frequency;
- division of the frequency of the carrier signal and production of at least four signal elements at the divided frequency and each with a different phase;
- periodical selection of one of the at least four signal elements;
- supply of the respectively selected signal to the transmission path and of a signal at the frequency of the at least four signal elements as a local oscillator signal to the reception path, or supply of a signal at the frequency of the at least four signal elements to the transmission path, and of the respectively selected signal as a local oscillator signal to the reception path;
- feedback of the signal emitted from the transmission path to the reception path;
- frequency-conversion of the signal emitted from the transmission path using the local oscillator signal;
- and
- determination of the amplitude of the frequency-converted signal.
A method for providing a divided frequency comprising the following steps:
- providing a clock signal;
- producing a plurality of signals at one frequency, each of the signals having a different phase with respect to each of the other signals;
- selecting a first and a second of the plurality of signals and providing a phase change at a respective switching time of the first and second signals.
Dependencies are inferred from the claim text.