Power savings mode for memory systems

A method, comprising:

• locking a delay locked loop in an electronic device at a first clock frequency;
• substantially instantaneously switching from said first clock frequency to a second clock frequency that is an integer multiple of said first clock frequency;
• operating said electronic device at said second clock frequency;
• and
• substantially instantaneously switching said second clock frequency to said first clock frequency when said electronic device is to be placed in a lower frequency mode.

A method, comprising:

• locking a delay locked loop in an electronic device at a first clock frequency;
• switching from said first clock frequency to a second clock frequency without slewing, wherein said second clock frequency is an integer multiple of said first clock frequency;
• operating said electronic device at said second clock frequency;
• and
• switching from said second clock frequency to said first clock frequency without slewing when electronic device is to be placed in a power saving mode.

An electronic device, comprising:

• a controller configured to generate a first clock signal having an adjustable frequency, wherein said adjustable frequency of said first clock signal includes a first frequency and a second frequency, wherein said second frequency is an integer multiple of said first frequency;
• and
• a delay locked loop coupled to receive said first clock signal as an input thereto from said controller, wherein said delay locked loop is configured to generate a second clock signal time-synchronized with said first clock signal and having an identical frequency as said first clock signal,
• wherein said controller is configured to provide said first clock signal with said first frequency to initially lock said first and said second clock signals at said first frequency in said delay locked loop, and wherein said controller is further configured to substantially instantaneously switch said first frequency of said first clock signal to said second frequency for an operating condition occurring after said initial lock is established in said delay locked loop.

An electronic device, comprising:

• a controller configured to generate a first clock signal having an adjustable frequency, wherein said adjustable frequency of said first clock signal includes a first frequency and a second frequency, wherein said second frequency is an integer multiple of said first frequency;
• and
• a delay locked loop coupled to receive said first clock signal as an input thereto from said controller, wherein said delay locked loop is configured to generate a second clock signal time-synchronized with said first clock signal and having an identical frequency as said first clock signal,
• wherein said controller is configured to provide said first clock signal with said first frequency to initially lock said first and said second clock signals at said first frequency in said delay locked loop, and wherein said controller is further configured to switch from said first frequency of said first clock signal to said second frequency without slewing for an operating condition occurring after said initial lock is established in said delay locked loop.

A system, comprising:

• a processor;
• a first bus;
• and
• a memory device coupled to said processor via said first bus, wherein said memory device includes:
• a plurality of memory cells to store data;
• and
• a plurality of peripheral devices for transferring data to and from said memory device, said peripheral devices comprising a delay locked loop initially locked at a first frequency of a first clock signal and configured to substantially instantaneously provide said first clock signal of a second frequency to facilitate a data read operation at one or more of said plurality of memory cells,
• wherein said second frequency is an integer multiple of said first frequency.

A system, comprising:

• a processor;
• a first bus;
• and
• a memory device coupled to said processor via said first bus, wherein said memory device includes:
• a plurality of memory cells to store data;
• and
• a plurality of peripheral devices for transferring data to and from said memory device, said peripheral devices comprising a delay locked loop initially locked at a first frequency of a first clock signal and configured to provide said first clock signal of a second frequency without slewing to facilitate a data read operation at one or more of said plurality of memory cells,
• wherein said second frequency is an integer multiple of said first frequency.