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US 2006/0233031 A1Published application
Synchronous RAM memory circuit
AssigneeInfineon Technologies AG
InventorAndreas Jakobs
Life of this patent
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Abstract
One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; and a reception strobe signal generating device which internally generates the reception strobe signal with synchronization with the received system clock signal.
Claims22
A random access memory (RAM) circuit, comprising:
- a plurality of memory cells which can be selectively addressed;
- a data connection for receiving and transmitting data;
- an address input for receiving address information for selecting memory cells;
- a command input for receiving commands;
- a clock input for receiving a system clock signal;
- an access control device which responds to the address information and to the commands which have been received in order to write received data to, and read data to be transmitted from, the memory cells which have been selected using the address information, under the control of the system clock signal;
- a reception sampling circuit for sampling the received data using an internally-generated reception strobe signal;
- a transmission sampling circuit for sampling the data to be transmitted using a transmission strobe signal;
- a transmission strobe signal generating device which generates the transmission strobe signal with synchronization to the received system clock signal;
- a reception strobe signal generating device which internally generates the reception strobe signal with synchronization to the received system clock signal, wherein the internally-generated reception strobe signal is provided to the reception sampling circuit;
- a bidirectional data clock signal port comprising:
- a data clock transmission device for transmitting the transmission strobe signal in parallel with the transmitted data, wherein the the transmission strobe signal is synchronized with a clock of the transmitted data;
- and
- a data clock reception device for receiving an external data clock signal which is synchronized with a clock of the received data;
- and
- a changeover device for selecting from one of:
- the internally-generated reception strobe signal derived from the received system clock signal;
- and
- the external data clock signal received via the bidirectional data clock signal port.
16 more elements
A memory circuit, comprising:
- a plurality of memory cells which can be selectively addressed;
- an access control device configured to selectively write received data to the plurality of memory cells and read stored data from the plurality of memory cells;
- a clock input for receiving a system clock signal;
- a reception sampling circuit for sampling received data to be written to the plurality of memory cells, wherein the reception sampling circuit is configured to utilize an internally-generated reception strobe signal;
- and
- a reception strobe signal generating device configured to generate the reception strobe signal based on the received system clock signal, wherein the internally-generated reception strobe signal is provided to the reception sampling circuit.
3 more elements
A memory system, comprising:
- a memory controller and a memory circuit,
- wherein the memory controller comprises:
- a clock signal output for providing a system clock signal;
- a bi-directional data connection for communicating data with the memory circuit;
- and
- a data clock signal connection for receiving a data clock signal from the memory circuit;
- wherein the memory circuit comprises:
- a plurality of memory cells which can be selectively addressed;
- an access control device configured to selectively write received data to the plurality of memory cells and read stored data from the plurality of memory cells;
- a clock input for receiving the system clock signal from the memory controller;
- a reception sampling circuit for sampling data, received from the memory controller, to be written to the plurality of memory cells, wherein the reception sampling circuit is configured to utilize an internally-generated reception strobe signal;
- and
- a reception strobe signal generating device configured to generate the reception strobe signal based on the received system clock signal, wherein the internally-generated reception strobe signal is provided to the reception sampling circuit.
10 more elements
A random access memory (RAM) circuit, comprising:
- a plurality of memory cells which can be selectively addressed;
- a data connection for receiving data to be written to the memory cells and transmitting data read from the memory cells;
- a clock input for receiving a system clock signal;
- a reception sampling circuit for sampling the received data at the data connection using an internally-generated reception strobe signal;
- and
- a reception strobe signal generating device which internally generates the reception strobe signal with synchronization to the received system clock signal, wherein the internally-generated reception strobe signal is provided to the reception sampling circuit.
3 more elements
A memory controller, comprising:
- a clock signal output for providing a system clock signal to a memory device having a reception strobe signal generating device configured to generate a reception strobe signal based on the received system clock signal, wherein the internally-generated reception strobe signal is provided to a reception sampling circuit configured to sample the received data using the internally-generated reception strobe signal;
- a bi-directional data connection for communicating data with the memory circuit;
- and
- a unidirectional data clock signal connection for receiving a data clock signal from the memory circuit;
- whereby data is provided to the memory without providing an external data clock signal to the memory circuit.
2 more elements
Dependencies are inferred from the claim text.