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US 2006/0233030 A1Published application
System and method for enhanced mode register definitions
AssigneeMicron Technology, Inc.
InventorJoo Choi
Life of this patent
Estimating the term…
Abstract
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with data selecting one option of a set of options for the operating mode. A second register is programmed with data selecting one of a plurality of sets of options for the operating mode. The data programmed in the first register selects one of the options of the set of options selected by the data programmed in the second register.
Claims45
A semiconductor memory receiving command signals, the memory comprising:
- a register configured to store data representative of selections for a plurality of memory operating options, the register having a plurality of mode registers, a first mode register of the plurality configured to store data corresponding to a selection from a set of selections for a first memory option, a second mode register of the plurality configured to store data corresponding to one of a plurality of sets of selections for the first memory option;
- and
- a command decoder coupled to the register and configured to decode the command signals and in response thereto generate internal control signals in accordance with the data stored in the register.
A command decoder for generating internal control signals in response to receiving command signals, the command decoder comprising:
- a first mode register configured to be programmed with data selecting an option from a respective set of options for a plurality of operating modes, each of the plurality of operating modes having a respective set of options;
- a second mode register configured to be programmed with data selecting one of a plurality of sets of options for at least one of the plurality of operating modes;
- and
- command decoder logic coupled to the first and second mode registers and configured to generate the internal control signals based on the command signals and the programmed data of the first and second mode registers.
1 more element
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a memory-cell array coupled to the address decoder and read/write circuit;
- and
- a control circuit coupled to the control bus, the address decoder, the memory-cell array and the read/write circuit, the control circuit having a command decoder for generating internal control signals in response to receiving command signals, the command decoder comprising:
- a first mode register configured to be programmed with data selecting an option from a respective set of options for a plurality of operating modes, each of the plurality of operating modes having a respective set of options;
- a second mode register configured to be programmed with data selecting one of a plurality of sets of options for at least one of the plurality of operating modes;
- and
- command decoder logic coupled to the first and second mode registers and configured to generate the internal control signals based on the command signals and the programmed data of the first and second mode registers.
9 more elements
A processor-based system, comprising
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
- and
- a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a memory-cell array coupled to the address decoder and read/write circuit;
- and
- a control circuit coupled to the control bus, the address decoder, the memory-cell array and the read/write circuit, the control circuit having a command decoder for generating internal control signals in response to receiving command signals, the command decoder comprising:
- a first mode register configured to be programmed with data selecting an option from a respective set of options for a plurality of operating modes, each of the plurality of operating modes having a respective set of options;
- a second mode register configured to be programmed with data selecting one of a plurality of sets of options for at least one of the plurality of operating modes;
- and
- command decoder logic coupled to the first and second mode registers and configured to generate the internal control signals based on the command signals and the programmed data of the first and second mode registers.
14 more elements
A method for programming operating modes for a memory having first and second mode registers, the method comprising:
- programming data in the second mode register to select one of a plurality of sets of options for a particular operating mode;
- and
- programming data in the first mode register to select one of the options of the selected set of options for the particular operating mode.
A method of increasing a number of selectable options for an operating mode of a semiconductor memory, the method comprising:
- providing a first register to be programmed with data selecting one option of a set of options for the operating mode;
- and
- providing a second register to be programmed with data selecting one of a plurality of sets of options for the operating mode, the data programmed in the first register selecting one of the options of the set of options selected by the data programmed in the second register.
Dependencies are inferred from the claim text.