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US 2006/0233029 A1Published application
Random access memory having voltage provided out of boosted supply voltage
AssigneeInfineon Technologies North America Corp.
InventorHelmut Seitz
Life of this patent
Estimating the term…
Abstract
A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply voltage and a reference voltage. The voltage source is configured to provide an output voltage out of the boosted supply voltage and based on the reference voltage.
Claims33
A random access memory, comprising:
- an array of single transistor memory cells;
- and
- a voltage source configured to receive a boosted supply voltage and a reference voltage and to provide an output voltage out of the boosted supply voltage and based on the reference voltage.
A random access memory, comprising:
- an array of random access memory cells;
- a voltage source configured to receive a boosted supply voltage and to provide an output voltage out of the boosted supply voltage, wherein the voltage source comprises:
- a first comparator configured to receive a first reference voltage and a first input voltage that is based on feedback from the output voltage and to compare the first reference voltage and the first input voltage and provide a first comparator output voltage;
- and
- a second comparator configured to receive a second reference voltage and a second input voltage that is based on feedback from the output voltage and to compare the second reference voltage and the second input voltage and provide a second comparator output voltage, wherein the voltage source regulates the output voltage out of the boosted supply voltage via the first comparator output voltage and the second comparator output voltage.
2 more elements
A random access memory, comprising:
- an array of random access memory cells, wherein each of the random access memory cells includes a transistor well configured to receive a back bias voltage;
- word lines crossing random access memory cells in the array of random access memory cells, wherein each of the word lines is configured to receive a word line voltage;
- and
- a voltage source configured to receive the word line voltage and regulate the back bias voltage out of the word line voltage, wherein the voltage source comprises:
- a first comparator configured to receive a first reference voltage and a first input voltage that is based on the back bias voltage and to compare the first reference voltage and the first input voltage and provide a first comparator output voltage;
- a first transistor configured to receive the word line voltage and the first comparator output voltage and to pull the back bias voltage toward the word line voltage based on the first comparator output voltage;
- a second comparator configured to receive a second reference voltage and a second input voltage that is based on the back bias voltage and to compare the second reference voltage and the second input voltage and provide a second comparator output voltage;
- and
- a second transistor configured to receive the second comparator output voltage and to pull the back bias voltage away from the word line voltage based on the second comparator output voltage.
6 more elements
A random access memory, comprising:
- means for storing data in an array of memory cells;
- means for receiving a boosted supply voltage and a reference voltage;
- and
- means for regulating an output voltage out of the boosted supply voltage and based on the reference voltage.
1 more element
A random access memory, comprising:
- means for storing data in an array of random access memory cells;
- means for regulating an output voltage out of a boosted supply voltage via a first comparison output voltage and a second comparison output voltage;
- means for receiving a first reference voltage and a first input voltage that is based on feedback from the output voltage;
- means for comparing the first reference voltage and the first input voltage to provide the first comparison output voltage;
- means for receiving a second reference voltage and a second input voltage that is based on feedback from the output voltage;
- means for comparing the second reference voltage and the second input voltage to provide the second comparison output voltage.
3 more elements
A method for providing a voltage in a random access memory, comprising:
- receiving a boosted supply voltage that provides word line bias in an array of random access memory cells;
- receiving a reference voltage;
- and
- regulating an output voltage that provides transistor well back bias in the array of random access memory cells out of the boosted supply voltage and based on the reference voltage.
1 more element
A method for providing a voltage in a random access memory, comprising:
- receiving a boosted supply voltage that provides word line bias in an array of random access memory cells;
- regulating an output voltage that provides transistor well back bias in the array of random access memory cells out of the boosted supply voltage via a first comparison output voltage and a second comparison output voltage;
- receiving a first input voltage that is based on feedback from the output voltage;
- comparing a first reference voltage and the first input voltage to provide the first comparison output voltage;
- receiving a second input voltage that is based on feedback from the output voltage;
- comparing a second reference voltage and the second input voltage to provide the second comparison output voltage.
3 more elements
A method for providing a back bias voltage in a random access memory, comprising:
- receiving a word line voltage in an array of random access memory cells;
- receiving a first reference voltage and a first input voltage that is based on the back bias voltage at a first comparator;
- comparing the first reference voltage and the first input voltage via the first comparator to provide a first comparator output voltage;
- receiving the word line voltage and the first comparator output voltage at a first transistor;
- pulling the back bias voltage toward the word line voltage based on the first comparator output voltage;
- receiving a second reference voltage and a second input voltage that is based on the back bias voltage at a second comparator;
- comparing the second reference voltage and the second input voltage via the second comparator to provide a second comparator output voltage;
- receiving the second comparator output voltage at a second transistor;
- and
- pulling the back bias voltage away from the word line voltage based on the second comparator output voltage.
7 more elements
Dependencies are inferred from the claim text.