System and method for a high-speed access architecture for semiconductor memory
OwnerChien-Hua Huanginventor
Life of this patent
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Abstract
A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is electrically connected to the first device by the first plurality of wires. The memory cell is electrically connected to the second device by a second plurality of wires. The second device is adapted to sense a small swing signal in the first plurality of wires, and to generate a full swing signal on the second set of wires in response to the small swing signal. The memory cell stores the full swing signal.
Claims20
A method for operating memory devices, the method comprising:
- generating a first small swing signal;
- transmitting the first small swing signal through a first plurality of wires;
- amplifying the first small swing signal to generate a full swing signal;
- and
- storing a state corresponding to the full swing signal into a memory cell.
A method for operating memory devices, the method comprising:
- reading from a memory cell to generate a first small swing signal;
- generating a second small swing signal from the first small swing signal;
- and
- transmitting the second small swing signal through a plurality of wires.
A method for operating a memory device, the method comprising:
- providing a memory cell;
- connecting transmission buffers to the memory cell, wherein the transmission buffers are configured to interface with the memory cell;
- and
- transmitting small swing signals between the transmission buffers and devices, wherein the small swing signals have magnitudes substantially smaller than a magnitude of a voltage supply of the memory device.
Dependencies are inferred from the claim text.