Redundancy circuits for semiconductor memory

A memory system comprising:

• a row interface circuit;
• a decoder circuit coupled to the row interface circuit;
• and
• a plurality of memory arrays, each of the plurality of memory arrays coupled to the decoder circuit and each further comprising:
• a plurality of world lines coupling a plurality of normal memory cells;
• at least one redundancy word line coupling a plurality of dummy memory cells;
• and
• a plurality of bit lines coupling the plurality of normal memory cells and dummy memory cells;
• wherein the row interface circuit controls the decoder circuit such that the decoder circuit accesses the at least one redundancy word line to form a redundant twin-cell structure.

A memory system comprising:

• a decoder circuit coupled to the row interface circuit;
• and
• a memory array coupled to the decoder circuit, the memory array further comprising:
• a plurality of world lines coupling a plurality of normal memory cells;
• and
• a redundancy word line coupling a plurality of dummy memory cells;
• wherein the decoder circuit accesses the redundancy word line to form a redundant twin-cell structure using two dummy memory cells.

A memory system comprising:

• a decoder circuit coupled to the row interface circuit;
• and
• a memory array coupled to the decoder circuit, the memory array further comprising:
• a plurality of world lines coupling a plurality of normal memory cells;
• and
• at least one redundancy word line coupling a plurality of dummy memory cells;
• wherein the decoder circuit accesses the redundancy word line to form at least one redundant twin-cell structure using one dummy memory cell and one normal memory cell.

A method of storing information in a semiconductor memory device having a memory array with normal memory cells and with dummy memory cells, the method comprising:

• running a test on the normal memory cells within the memory array in order to detect a defective normal memory cell;
• identifying a word line associated with the defective normal memory cell;
• disabling the word line associated with the defective normal memory cell;
• and
• enabling dummy memory cells configured as twin-cells in place of the defective normal cell.

A method of storing information in a semiconductor memory device having a memory array with normal memory cells and with dummy memory cells, the method comprising:

• running a test on the normal memory cells within the memory array in order to detect a defective normal memory cell;
• identifying a word line associated with the defective normal memory cell;
• and
• coupling the word line associated with the defective normal memory cell with a redundancy word line associated with dummy memory cells such that twin-cells are configured comprising at least one normal memory cell and one dummy memory cell.

A memory cell array comprising:

• a plurality of word lines and a plurality of bit lines;
• at least one redundancy word line;
• at least some of the plurality of word lines and at least some of the plurality of bit lines intersecting at a plurality of normal memory cells, thereby providing access to the plurality of normal memory cells via at least some of the plurality of word lines and at least some of the plurality of bit lines;
• and
• the at least one redundancy word line and at least some of the plurality of bit lines intersecting at a plurality of dummy memory cells, thereby providing access to the plurality of dummy memory cells via the at least one redundancy word line and at least some of the plurality of bit lines;
• wherein at least one dummy memory cell is combined with another memory cell to form a twin-cell structure for single-bit storage.