Semiconductor storage device having a plurality of stacked memory chips

A semiconductor storage device comprising:

• a base substrate having a command/address external terminal group to which command signals and address signals are supplied and a single chip select external terminal to which a chip select signal is supplied;
• an interface chip that is mounted on the base substrate and is connected to the command/address external terminal group and the chip select external terminal;
• and
• a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations,
• wherein said interface chip can individually activate said plurality of memory chips based on said address signals and said chip select signal.

A semiconductor storage device comprising:

• a base substrate having a command/address external terminal group to which command signals and address signals are supplied and a single chip select external terminal to which a chip select signal is supplied;
• and
• a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations,
• wherein one of said plurality of memory chips is connected to the command/address external terminal group and the chip select external terminal and can individually activate said plurality of memory chips based on said address signals and said chip select signal.