Surge detector/counter

Abstract

A combination surge detector/counter device that detects and counts various surge conditions that occur during a specified time interval. The device includes a surge detector circuit which generates a surge voltage signal in response to the occurrence of a surge condition at an input AC power source. The surge detector includes a surge suppressor, such as a metal oxide varistor (MOV), coupled in series with a current sensor such as a toroid transformer. In response to a surge condition, the surge suppressor generates a surge current signal which is converted into a surge voltage signal by the current sensor. To improve the sensitivity of the detector, a portion of a lead of the surge suppressor may be arranged to extend through a central opening of the current sensor. The surge voltage signal is processed by a surge sensitivity selector which provides a plurality of user selectable voltage sensitivity levels. A surge sensitivity circuit further processes the surge voltage signal from the sensitivity circuit to determine a count of the number of occurrences of surges or surge conditions at the input of the detector. A storage means such as a capacitor can be used to store the count-value even after the device is disconnected from the AC power source. A display means can be coupled to the output of the device to display the number of occurrences of surge conditions.

Dependencies are inferred from the claim text.