Circuit structure for dual resolution design
AssigneeToppoly Optoelectronics Corp.
InventorSzu-Hsien Lee
Life of this patent
Estimating the term…
Abstract
A dual resolution circuit for supporting normal resolution display mode and half resolution display mode is disclosed. In the dual resolution circuit, cascaded shift registers are controlled by a group of clock signals to generate intermediate scan signals in response to a start pulse. A normal/reverse scan switch, controlling a normal scan mode and a reverse scan mode, feeds back the intermediate scan signal from one shift register to another shift register. A dual resolution switch switches signal paths of the intermediate scan signals to logic gates. The logic gates perform logic operation on an enablement signal and the intermediate scan signals to generate final scan signals used in dual resolution display modes.
Claims14
A dual resolution circuit for supporting dual resolution display modes in a display apparatus, comprising:
- a shift register stage, receiving a start pulse and at least four clock signals, generating a plurality of intermediate scan signals;
- a dual resolution switch, controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals;
- and
- a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes.
A display panel, comprising:
- a dual resolution circuit for supporting dual resolution display modes in the display panel, the dual resolution circuit including:
- a clock generator, generating at least four clock signals;
- a shift register stage, receiving a start pulse and at least four clock signals for generating a plurality of intermediate scan signals;
- a normal/reverse scan switch, receiving a normal scan signal, a reverse scan signal and the start pulse, for controlling a normal scan or a reverse scan of the display panel;
- a dual resolution switch, being controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals;
- and
- a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes in the display panel.
An electronic device having a display panel, the display panel including:
- a dual resolution circuit for supporting dual resolution display modes in the display panel, the dual resolution circuit including:
- a clock generator, generating at least four clock signals;
- a shift register stage, receiving a start pulse and at least four clock signals for generating a plurality of intermediate scan signals;
- a normal/reverse scan switch, receiving a normal scan signal, a reverse scan signal and the start pulse, for controlling a normal scan or a reverse scan of the display panel;
- a dual resolution switch, being controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals;
- and
- a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes in the display panel.
Dependencies are inferred from the claim text.