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US 2006/0232450 A1Published application
Decode circuitry and a display device using the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsRyuichi Hashido, Hiroyuki Murai
Life of this patent
Estimating the term…
Abstract
Multi-bit input data is divided into at least a first bit group and a second bit group, and each of first sub-decode circuits selects one selection target signal/voltage from selection target signal/voltage group in accordance with the first bit group. Then, one signal/voltage is selected according to the second bit group from the signals/voltages selected by the first sub-decode circuits, and is transmitted to an output signal line. Each of second sub-decode circuits is formed of a single train of series switches, and only one of the switch train is made conductive to transmit a finally selected signal/voltage to the output signal line.
Claims10
Decode circuitry for decoding a multi-bit digital data and outputting an electric signal indicating a decoding result, comprising:
- a first bit group decode circuit arranged corresponding to a first bit group of said multi-bit digital data of a multiplicity of bits, and decoding said first bit group, said multi-bit digital data being divided into a plurality of bit groups at least one of which includes plural bits, the bit groups including said first bit group, said first bit group decode circuit including a plurality of first sub-decode circuits arranged corresponding to respective sets each including a plurality of output candidates, and said first sub-decode circuits commonly receiving the bit or bits of said first bit group and each first sub-decode circuit selecting one output candidate from a corresponding set of the output candidates;
- and
- a second bit group decode circuit arranged corresponding to a second bit group of said multi-bit digital signal of the multiplicity of bits, and decoding the bit or bits of said second bit group to select an output of said first bit group decode circuit for outputting the electric signal indicating a decode result, said second bit group decode circuit including a plurality of second sub-decode circuits arranged corresponding to the first sub-decode circuits, and commonly receiving said second bit group to select the outputs of corresponding first sub-decode circuits for outputting selected outputs to an output line, respectively, each second sub-decode circuit including a series connection body of switching element or elements provided for the bit or bits of the second bit group and being selectively made conductive in response to the respective bit or bits in said second bit group, the series connection bodies of the second sub-decode circuits being commonly coupled to said output line, and the electric signal indicating said decoding result being supplied to said output line.
A display device comprising:
- at least one digital-to-analog conversion circuit for converting display pixel data represented by multi-bit digital data of multiple bits to an analog voltage, said digital-to-analog converter circuit including (i) a first bit group decode circuit arranged corresponding to a first bit group of said multi-bit digital data and decoding said first bit group, said multi-bit digital data being divided into a plurality of bit groups at least one of which includes plural bits, the bit groups including said first bit group, said first bit group decode circuit including a plurality of first sub-decode circuits arranged corresponding to respective sets each including a plurality of output candidates, and commonly receiving the bit or bits of said first bit group, each first sub-decode circuit selecting one output candidate from a corresponding set of the output candidates, and (ii) a second bit group decode circuit arranged corresponding to a second bit group of said multi-bit digital signal of the multiple bits, and decoding the bit or bits of said second bit group to select an output of said first bit group decode circuit and output an electric signal indicating a decode result, said second bit group decode circuit including a plurality of second sub-decode circuits, arranged corresponding to said first sub-decode circuits and commonly receiving the bit or bits of said second bit group, each for selecting an output of a corresponding first sub-decode circuit and outputting a selected output to an output line, each second sub-decode circuit including a series connection body of switching element or elements provided for the respective bit or bits of the second bit group and being selectively made conductive in response to the bit or bits in said second bit group, the series connection bodies of the second sub-decode circuits being commonly coupled to said output line, and the analog voltage signal indicating the decoding result being supplied to said output line;
- a plurality of data lines each coupled to a plurality of display pixels;
- and
- a data line drive circuit for driving the data lines according to the analog voltage supplied from said at least one digital-to-analog conversion circuit.
1 more element
Dependencies are inferred from the claim text.