Control circuit for command signals of clock generator

A control circuit for command signals of a clock generator comprising a power supply end, an output end, a control end, a first resistor, a second resistor, and a switch, the first resistor, the second resistor and the switch connected in series between the power supply end and the ground, the control end connected to a node between the diode and the second resistor, the output end connected to a node between the diode and the first resistor, wherein the output end outputs the command signals to the clock generator, when the voltage at the control end is at a high level, the switch is turned off to output a high voltage at the voltage output end, when the voltage at the control end is at a low level, the switch turned on to output a low voltage at the voltage output end.