# US 2006/0232323 A1 · Circuit and method for stable fuse detection

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- Number: US 2006/0232323 A1
- Document ID: US20060232323A1
- Status: Published application
- Kind: A1
- Application number: 11/106,100
- Filed: 2005-04-14
- Published: 2006-10-19
- Earliest claimed: 2005-04-14
- Assignees: Micron Technology, Inc.
- Inventors: Christian Mohr; Scott Smith
- Web page: https://patentgrep.com/patent/US20060232323A1

## CPC

- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal that whose state is recoverable from to a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

## Claims

### Claim 1

A fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 2 (depends on 1)

The fuse state detection circuit of claim 1 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 3 (depends on 1)

The fuse state detection circuit of claim 1 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 4 (depends on 1)

The fuse state detection circuit of claim 1 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 5

A fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event.

### Claim 6 (depends on 5)

The fuse state detection circuit of claim 5 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 7 (depends on 5)

The fuse state detection circuit of claim 5 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 8 (depends on 5)

The fuse state detection circuit of claim 5 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 9 (depends on 5)

The fuse state detection circuit of claim 5 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 10

A fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse.

### Claim 11 (depends on 10)

The fuse state detection circuit of claim 10 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 12 (depends on 10)

The fuse state detection circuit of claim 10 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 13 (depends on 10)

The fuse state detection circuit of claim 10 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 14 (depends on 10)

The fuse state detection circuit of claim 10 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 15

A method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting.

### Claim 16 (depends on 15)

The method of claim 15 additionally comprising monitoring the condition of said pair of fuse elements and producing an output signal that whose state is recoverable from a negative triggering event.

### Claim 17 (depends on 16)

The method of claim 16 wherein said output signal assumes a first logic state when a first fuse element is blown and a second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 18 (depends on 15)

The method of claim 15 additionally comprising monitoring the condition of said pair of fuse elements and producing an output signal that resolves itself to the correct state without the need for a reset pulse.

### Claim 19 (depends on 18)

The method of claim 18 wherein said output signal assumes a first logic state when a first fuse element is blown and a second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 20

A method of operating a fuse state detection circuit, comprising:
monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 21

A method of operating a fuse state detection circuit, comprising:
monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that is responsive to the states of said first and said second fuse elements and whose state is resistant to a negative triggering event.

### Claim 22 (depends on 21)

The method of claim 21 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 23

A method of operating a fuse state detection circuit, comprising:
monitoring the state of a first fuse element;
monitoring the state of a second fuse element; and
producing an output signal that is responsive to the states of said first and said second fuse elements and resolves itself to the correct state without the need for a reset pulse.

### Claim 24 (depends on 23)

The method of claim 23 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 25

A memory device, comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 26 (depends on 25)

The memory device of claim 25 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 27 (depends on 25)

The memory device of claim 25 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 28 (depends on 25)

The memory device of claim 25 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 29

A memory device, comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event.

### Claim 30 (depends on 29)

The memory device of claim 29 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 31 (depends on 29)

The memory device of claim 29 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 32 (depends on 29)

The memory device of claim 29 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 33 (depends on 29)

The memory device of claim 29 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 34

A memory device, comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse.

### Claim 35 (depends on 34)

The memory device of claim 34 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 36 (depends on 34)

The memory device of claim 34 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 37 (depends on 34)

The memory device of claim 34 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 38 (depends on 34)

The memory device of claim 34 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 39

A system, comprising:
a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal assuming a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 40 (depends on 39)

The system of claim 39 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 41 (depends on 39)

The system of claim 39 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 42 (depends on 39)

The system of claim 39 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 43

A system, comprising:
a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements so as to produce an output signal whose state is resistant to a negative triggering event.

### Claim 44 (depends on 43)

The system of claim 43 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 45 (depends on 43)

The system of claim 43 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 46 (depends on 43)

The system of claim 43 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 47 (depends on 43)

The system of claim 43 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.

### Claim 48

A system, comprising:
a processor;
a memory device; and
a bus for connecting said processor to said memory device, said memory device comprising:
an array of memory cells;
a plurality of peripheral devices for reading data out of and writing data into said array of memory cells, said peripheral devices comprising:
a fuse state detection circuit, comprising:
a first fuse element;
a second fuse element; and
circuitry responsive to said first and second fuse elements for producing an output signal capable of resolving itself to the correct state without the need for a reset pulse.

### Claim 49 (depends on 48)

The system of claim 48 wherein said output signal assumes a first logic state when said first fuse element is blown and said second fuse element is unblown and a second logic state when said first element is unblown and said second element is blown.

### Claim 50 (depends on 48)

The system of claim 48 wherein said circuitry comprises a first inverter and a second inverter, each responsive to said first fuse element, and a logic gate responsive to a control signal and to one of said second fuse element and said second inverter, wherein said first inverter is responsive to an output of said logic gate and wherein said output signal of said fuse state detection circuit is responsive to said first inverter.

### Claim 51 (depends on 48)

The system of claim 48 additionally comprising a first address line for addressing said first fuse element and a second address line for addressing said second fuse element.

### Claim 52 (depends on 48)

The system of claim 48 wherein at least one of said first fuse element or said second fuse element include one of a laser fuse, an anti-fuse, and a transistor.